This paper explains how nanoprobe analysis was used to determine the cause of data retention failures in nonvolatile memory (NVM) bitcells. The challenge with such memory cells is that they consist of two transistors with a single control gate in series with a programmable floating gate connected by a shared source/drain active area. With such a layout, there is no way to isolate the control gate from the floating gate, meaning that characterization must be performed simultaneously on both transistors. Having to characterize two transistors connected in series increases the number of potential electrical signature effects not by a factor of two, but rather the power of two, which makes interpreting the results much more difficult. As discussed in the paper, however, the authors used an atomic force probe to verify the bit map of the faulty device and then analyze the failing bit to confirm the programming error and reveal the possible failure mechanism. The failure mechanism was determined based on its electrical signature and a physical analysis of the bitcell location.

This paper presents a number of case studies in which various methods and tools are used to localize resistive open defects, including two-terminal IV, two-terminal electron-beam absorbed current (EBAC), electron beam induced resistance change (EBIRCH), pulsed IV, capacitance-voltage (CV) measurements, and scanning capacitance microscopy (SCM). It also reviews the advantages and limitations of each technique.

This paper demonstrates a novel defect localization approach based on EBIRCH isolation conducted from the backside of flip chips. It discusses sample preparation and probing considerations and presents a case study that shows how the technique makes it possible to determine the root cause of subtle defects, such as bridging, in flip chip failures.

An experimental study was undertaken to determine the minimum level of leakage or shorting current that could be detected by electron-beam induced resistance change (EBIRCH) analysis. A 22-nm SRAM array was overstressed with a series of gradually increasing voltage biases followed by EBIRCH scans at 1 V and 2-kV SEM imaging until fins were observed. It was found that the fins of a pulldown device could be imaged by EBIRCH at just 12 nA of shorting current, representative of a soft failure. Stressing the sample at higher voltages eventually created an ohmic short, which upon further investigation, strongly suggested that the Seebeck effect plays a significant role in EBIRCH analysis.

In this paper, we describe the difference between oscilloscope pulsing tests and waveform generator fast measurement unit (WGFMU) tests in analyzing high-resistance defects in DRAM main cells. Nanoprobe systems have various constraints in terms of pulsing whether it involves an oscilloscope or pulse generator. There are certain types of devices, such as DRAM cells, for which these systems are ineffective because saturation currents are too small. In this paper, we address this constraint and propose a new way to conduct pulsing tests using the WGFMU's arbitrary linear waveform generator in combination with an electro-optical nanoprobe.

In order to understand and communicate a PFA strategy during an analysis, a two-dimensional diagram of the layout of a suspect net has been developed. Net connections are extracted from the layout and drawn in a two-dimensional stitch diagram. The result is a simplified diagram providing a stack view of the layout layers for the net(s) of interest. Key analysis decisions are made and communicated using the stitch diagram. Using this diagram, selective nanoprobe measurements are made. Software implementation that extracts and draws the diagram allows for faster creation as well as making larger nets practical. As examples show, nanoprobe curve trace analysis using a simplified diagram has proven to be a successful evidence based approach to physical failure analysis of complex nets.

For advanced node semiconductor process development, manufacturing, fault isolation and product failure analysis, nanoprobing is an indispensable technology. As the process technology node scales, transistors and materials used are more susceptible to electron beam damage and changes. As scanning electron microscope (SEM) energy decreases to minimize electron beam damage, imaging resolution degrades. Process scaling has not only affected patterning dimensions and pitch scaling, but also materials utilized in advanced nodes. The material used at the contact level has changed from tungsten (W) to cobalt (Co), in combination with ultra-low K dielectrics. These new materials tend to make sample preparation and probing increasingly more challenging. At advanced nodes with sub-20nm contacts, probe landing accuracy and probe-contact stability are important to maintain good electrical contact throughout measurement time. In this paper, we discuss nanoprobing results from a 7nm SRAM obtained from a commercially available leading edge 7nm SOC.

The global radio frequency (RF) semiconductor market size is growing dramatically in recent years, especially with the growing demand for mobile devices, communication networks, automotive applications, etc. Failure analysis (FA) on RF devices is normally more complex than digital devices, especially when it involves soft failure. This paper discusses FA on an RF product soft failure issue by the pulsed currentvoltage (IV) nanoprobing technique. The device suffered from high-frequency failure and exhibited abnormal repetitive softstart signature. Previous publications on pulsed IV nanoprobing applications were mostly related to Front End Of Line (FEOL) issues and simulations. In most of these cases, the electrical abnormality could also be observed with normal DC IV measurement. In this paper, the pulsed IV nanoprobing was performed at the Back End Of Line (BEOL) interconnects to isolate the failure that was otherwise not detected with normal DC nanoprobing or the reported pulse IV measurement. The proposed method successfully isolate, simulate the failure, and helping us to identify the process and design rule weakness.

Nanoprobing systems have evolved to meet the challenges from recent innovations in the semiconductor manufacturing process. This is demonstrated through an exhibition of standard SRAM measurements on TSMC 7 nm FinFET technology. SEM based nanoprober is shown to meet or exceed the requirements for measuring 7nm technology and beyond. This paper discusses in detail of the best-known methods for nanoprobing on 7nm technology.

Non-volatile memory is the most important memory device in IC chips. As a memory, embedded non-volatile memory (NVM) is a fundamental structure in many kinds of semiconductor devices. It is commonly used in the modern electrical appliance as a code or data memory. For different applications, there are different memory designs or IP, like ROM, OTP, Flash, MRAM, PCRAM etc. The physical mechanism of these NVMs are different, some are electron based, some are resistance based and fuse or anti-fused based. The experiment described in this paper is performed on an electron charge storage based NVM. That means a medium is employed to store electron charge to differentiate two statuses “0” and “1”. Floating Poly gate is this medium used as electron charge storage in this NVM. Since the storage medium is in floating condition, it cannot be accessed externally. The methods of performing direct analysis are limited for this kind of device, especially in the case of subtle defects or soft fail. As semiconductor devices scale, the defects become smaller and more subtle. Nanoprobing is usually the only way to find the defect location electrically before any further physical analysis. In this experiment, the single bit NVM fail was analyzed. Different PFA methods used during the analysis, failed to find the defect. Nanoprobing was employed to precisely isolate the defect. Key word: nanoprobing, NVM, subtle defect, Poly-crystalline, floating gate

Reliability tests, such as Time-Dependent Dielectric Breakdown (TDDB), High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Those reliability tests are more stringent and complex especially for automotive Complementary Metal–Oxide–Semiconductor (CMOS) devices, this because it involves human lives and safety. In foundries failure analysis (FA), Transmission Electron Microscopy (TEM) analysis often required in order to provide insights into the defect mechanisms and the root cause of the reliability tests. In this paper, application of high resolution Nano-probing Electron Beam Absorbance Current (EBAC), Nano-probing active passive voltage contrast (APVC), and TEM with Energy Dispersive X-Ray Spectroscopy (EDX) to identify the failing root cause of Inter- Poly Oxide (IPO) TDDB failure on an automotive grade Non- Volatile Memory (NVM) device was investigated. We have successfully demonstrated that TEM analysis after Nanoprobing EBAC/APVC fault isolation is an effective technique to reveal the failure root cause of IPO breakdown after reliability stresses.

This paper presents Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) on a random time zero (t0) gate oxide defect within an IBM processor manufactured with a 14nm SOI (Silicon On Insulator) FinFET technology. The natures of the Functional Fail, the gate oxide defect, and the transistor characteristics are included. The impact of this gate oxide defect to product yield and performance, plus the extent to which it extends across the product chip, which includes passing circuits, is covered. Since chips, which may contain this defect, could be present within the entire product lifecycle, the reliability aspects of the defect at the transistor level were investigated. Among the various reliability stresses available for transistors, Constant Voltage Stress (CVS) Bias Temperature Instability (BTI) was chosen. CVS BTI stressing was able to be performed on both the NFETs and PFETs within the Inverter of the failing circuit, plus other identical reference circuits. The BTI stress nanoprobing is covered. This includes an overview of BTI stressing, confirming the nanoprobing system and electrical stress/test programs are adequate for BTI stressing, BTI stress methodologies for Inverters, plus the BTI stress results. The transistor level BTI stress results are discussed and compared to other published BTI literature. Finally, the reliability aspects of this gate oxide defect are discussed.

This paper demonstrates capacitance-voltage (CV) measurements using Nanoprobing to characterize different fails and better understand the defect mode. Three case studies are conducted using the CV technique. DC Nanoprobing measurements are first used to identify the failure mode. Subsequently, CV measurements are employed to further narrow down the root cause, to understand the process mechanism leading to the failure. A pathway to use the CV technique to isolate defects with-in a device under test is also demonstrated. It has been shown that the gate to lightly doped drain CV measurements will be a very useful characterization tool to understand various fail modes. This finding, along with DC measurement, serves to narrow the issue primarily to gate stack work function related matters.

Root cause analysis of parametric failures in mixed-signal IC designs has been a challenging topic due to the marginality of failure modes. This work presents two case studies of offset voltage (Vos) failures which are commonly seen in mixed-signal IC designs. Nanoprobing combined with Cadence simulation becomes a powerful methodology in fault isolation. Large Vos is typically caused by the mismatch of electrical properties of the components on two balanced rails. In our first case, we present a case-study of nanoprobing combined with bench test and Cadence simulation to debug the root cause of a class-D amplifier voltage offset related yield loss from mixedsignal design sensitivity. Bench electrical measurements confirm the dependency of offset voltage (Vos) on boost voltage (VBST) and amplifier gain settings, which isolates the root cause from mismatch in amplifier gain resistors. The bench measurements match extremely well when an extra parasitic resistance is added to the input of the amplifier in the Cadence simulation. Kelvin 4 points nanoprobing on the amplifier input matching resistors confirmed a 40% mismatch as a result of both layout sensitivity and fabrication. This case highlights that the role of nanoprobing combined with Cadence simulation is not only valuable in physical failure root cause analysis but also in providing guidance to a potential process fix for current and future designs. In our second case, a decrease in offset voltage (Vos) is found through bench validation by reducing the supply voltage (VDD), suggesting a new mismatch mechanism related to the body-source bias. Nanoprobing of the input PMOS transistors clearly shows humps in the subthreshold region of IV characteristics, and the severity of humps increases with body-source bias. Vos derived from the nanoprobing results aligns well with the bench data, suggesting hump effect to be the root cause of Vos deviation. This study suggests that by combining Cadence simulation and nanoprobing in the failure analysis process of parametric failures, suspicious problematic devices can be identified more easily, greatly reducing the need for trial and error.

This paper demonstrates a two-pin Electron Beam Induced Current (EBIC) isolation technique to isolate the defective Fin with gate oxide damage in advanced Fin Field Effect Transistor (FinFET) devices. The basic principle of this twopin configuration is similar to two-point Electron Beam Absorption Current (EBAC) technique: a second pin as ground on the gate is added to partially shunt the EBIC current and thus creates EBIC contrast from the defective Fin. In this way, the challenge of highly resistive short path inside the Fin in a narrow gate can be overcome. The paper will provide failure analysis details using this technique for defective Fin isolation.

This paper analyzes the through-put time and output of fault isolation and failure analysis (FI/FA) flows on state-of-the-art microprocessors. An average reduction in through-put time of 40% was demonstrated with a shortened FI/FA flow while still maintaining a high success rate. The direct FA/nano-probing flow which was utilized by up to around 90% of the fail cases omitted the optical fault isolation step and instead expanded the use of plasma FIB, nano-probing and electrical isolation techniques (such as diagnosis tools). The end result is shorter through-put time and higher FI/FA volume which is important in order to achieve a faster production ramp. In the paper two cases studies are presented to demonstrate the new efficient FI/FA techniques.

As advanced silicon-on-insulator (SOI) technology becomes a more widespread technology offering, failure analysis approaches should be adapted to new device structures. We review two nanoprobing case studies of advanced SOI technology, detailing the electrical characterization of a compound gate-to-drain defect as well as the characterization of unexpected SOI source-to-well leakage.

The paper reports the investigation on the root cause of source-drain leakage in bulk FinFET devices. While the failing device was readily isolated by nanoprobing technique and the electrical analysis pinpointed the potential defect location inside the Fin channel, the identification of physical root cause went through extreme challenges imposed by the tiny-sized device and the unique FinFET 3D architecture. The initial TEM analysis was misled by the projection of a species in the lamella surface and thus could not explain the electrical data. Careful analysis on the device structure was able to identify the origin of the species and led to the discovery of the actual root cause. This paper will provide the analysis details leading to the findings, and highlight the role of electrical understanding in not only providing guidance for physical analysis but also revealing the true root cause of failure in FinFET devices.

In this paper, we demonstrate a novel nanoprobing approach to establish cause-and-effect relationships between voltage stress and end-of-life performance loss and failure in SRAM cells. A Hyperion II Atomic Force nanoProber was used to examine degradation for five 6T cells on an Intel 14 nm processor. Ten minutes of asymmetrically applied stress at VDD=2 V was used to simulate a ‘0’ bit state held for a long period, subjecting each pullup and pulldown to either VDS or VGS stress. Resultant degradation caused read and hold margins to be reduced by 20% and 5% respectively for the ‘1’ state and 5% and 2% respectively for the ‘0’ state. ION was also reduced, for pulldown and pullup respectively, by 4.5% and 5.4% following VGS stress and 2.6% and 33.8% following VDS stress. Negative read margin failures, soft errors, and read time failures all become more prevalent with these aging symptoms whereas write stability is improved. This new approach enables highly specific root cause analysis and failure prediction for end-of-life in functional on-product SRAM.

Nanoprobing, electrical probing (DC electrical measurement of semiconductors using nanoscale probes) on an electron microscopic scale, and EBAC, a high-resolution, static technique, can be used for isolating defects and improving failure analysis success rates on both logic and SRAM devices. This paper presents three case studies of subtle defects on a technology beyond 14nm that required nanoprobing.