SRAM is often chosen to be the process qualification vehicle during technology development or yield learning vehicle during product manufacturing, and consequently failure analysis of SRAM is the main feedback for process improvement and yield learning. The most common SRAM failure is single bit cell failure. Although its location can be precisely localized by functional test and the defect causing the failure is within the failing bit cell, its failure analysis becomes more and more challenging in advanced technology nodes. As semiconductor technology continuously scales down, SRAM bit cell size and power supply voltage decrease, resulting in increased transistor strength variation and mismatch. SRAM single bit cell soft failures have become more and more common. For such a failure, its defect is usually subtle or even there is not physical defect at most cases. The soft failure is just due to transistor parameter variation. To evaluate the single bit cell soft failure and identify its root cause, electrical nano-probing is an indispensable measure. In this paper, we will first describe the operation of a 6-Transistor (6-T) SRAM single bit cell and three different types of single bit cell soft failures, then discuss the two electrical nano-probing methods for the SRAM single bit cell soft failure.

Wordline defects in 3D Replacement Gate NAND (RG NAND) are a major issue holding back part functionality and yield. Shorted wordline locations isolated by EBIRCH enable precise lamella preparation for STEM/TEM, increasing the defect visual rate for physical failure analysis. Due to deprocessing limitations, such as specialized tool requirements, part-specific die preparation knowledge, and the location of the defect in the die, makes preparing samples for successful EBIRCH isolation difficult and time-consuming. A novel sample preparation method for SEM-based nanoprobing has been developed to solve these issues, enabling EBIRCH/EBAC for isolating wordline defect locations with minimal advanced deprocessing and which can be similarly applied to any RG NAND node.

The escalating demand for embedded non-volatile memories (NVM) across automotive, mobile, and personal computer applications necessitates continuous innovation in semiconductor devices. This study focuses on the failure analysis (FA) of split-gate NVM memory, which dominates the landscape of embedded NVM in advanced processes. Presenting a novel approach utilizing nanoprobe techniques on non-accessible floating gate (FG) of NVM, we aim to detect leakage pathways through electron beam absorb current (EBAC) analysis. Through comprehensive experimental analysis and case studies, we demonstrate the efficacy of electrical nanoprobing and innovative sample preparation techniques in understanding the mechanisms behind program and data retention failures in NVM. Our study highlights the significance of precise delayering and nanoprobe techniques on inaccessible FG and identifies potential avenues for future FA methodologies. These findings contribute to a deeper understanding of NVM failure mechanisms, paving the way for enhanced reliability or yield in NVM devices.

Soft defects—failures that manifest only under specific voltage, temperature, or frequency conditions—require specialized fault isolation techniques for accurate characterization. This paper demonstrates thermal response failure localization using scanning electron microscope (SEM) nanoprobing with an integrated thermal stage. While nanoprobing typically serves as the final step in fault isolation failure analysis (FIFA), thermal nanoprobing is essential for characterizing temperature-dependent parametric defects by enabling measurements at both passing and failing temperatures. We present three case studies: a "worse at cold" failure reproduction, a parametric root cause identification through thermal characterization, and a complex thermal failure that was uniquely isolatable through thermal nanoprobing. These cases illustrate the technique's effectiveness in analyzing temperature-dependent defects that occur outside room temperature conditions.

This work employs an easy-to-use method to quickly find and characterize leakage currents on a semiconductor sample by combining electrical fault isolation and electrical measurements. By using a simple add-on for a probing system’s tip holders, a prober is transformed into a scanning device that measures currents through a sample’s surface and visualizes the currents in a 2D color map that can be superimposed onto the SE image. As a case study, an area of 1.5 µm x 1.5 µm of a 3 nm device was scanned while the current through the contacts was measured and visualized with Current Imaging (CI) and gate currents were characterized. One leaking gate could be identified and the position of the failure was localized using Electron Beam Induced Resistance CHange (EBIRCH) imaging. This technique also avoids any damage caused by electron beam irradiation as the beam can be switched off during scanning.

In this paper, the failure analysis of InGaAs/GaAs-on-Si nanoridge laser diodes using the electron beam based nano-probing technique is presented. These III-V laser devices are fabricated using the nano-ridge engineering approach where the misfit dislocations generated during the growth of InGaAs/GaAs layers on silicon substrate are confined away from the active region. It is observed that the applied electrical stress causes degradation of electrical properties of the laser devices. We demonstrate the application of the electron beam induced current (EBIC) technique for failure analysis of nano-ridge lasers. This high-resolution technique helps to visualize the local distribution of the electric field in a nano-ridge p-i-n diode. The EBIC signal from the reference (electrically unstressed) device and the electrically stressed device is compared and hence can be used to identify the defective region. Furthermore, in-situ electrical stress experiments are performed for systematic analysis of the impact of electrical stress on the EBIC results.

The effects of sample prep with a Ga + -ion Focused Ion Beam (Ga-FIB) on measurements of electron beam induced current (EBIC) were studied. Concerns have been occasionally raised about amorphization from the beam, or even Ga + implantation ruining the ability to make useful measurements for purposes of either failure analysis or device tailoring. To understand the magnitude of any deleterious effects, two different lamellae from a 5 nm SRAM sample were prepared with different areas of increasingly improved polish, as indicated by decreasing, cumulative, FIB beam energy, followed by EBIC measurements at 1 or 2 kV beam landing energy. A first experiment looked at the ability to generate EBIC measurements from depletion zones and found no difference across the various beam polish cells. A second experiment considered leakage and/or shorts and found little problematic currents, within standard deviations.

This paper explains how nanoprobe analysis was used to determine the cause of data retention failures in nonvolatile memory (NVM) bitcells. The challenge with such memory cells is that they consist of two transistors with a single control gate in series with a programmable floating gate connected by a shared source/drain active area. With such a layout, there is no way to isolate the control gate from the floating gate, meaning that characterization must be performed simultaneously on both transistors. Having to characterize two transistors connected in series increases the number of potential electrical signature effects not by a factor of two, but rather the power of two, which makes interpreting the results much more difficult. As discussed in the paper, however, the authors used an atomic force probe to verify the bit map of the faulty device and then analyze the failing bit to confirm the programming error and reveal the possible failure mechanism. The failure mechanism was determined based on its electrical signature and a physical analysis of the bitcell location.

This paper presents a number of case studies in which various methods and tools are used to localize resistive open defects, including two-terminal IV, two-terminal electron-beam absorbed current (EBAC), electron beam induced resistance change (EBIRCH), pulsed IV, capacitance-voltage (CV) measurements, and scanning capacitance microscopy (SCM). It also reviews the advantages and limitations of each technique.

This paper demonstrates a novel defect localization approach based on EBIRCH isolation conducted from the backside of flip chips. It discusses sample preparation and probing considerations and presents a case study that shows how the technique makes it possible to determine the root cause of subtle defects, such as bridging, in flip chip failures.

An experimental study was undertaken to determine the minimum level of leakage or shorting current that could be detected by electron-beam induced resistance change (EBIRCH) analysis. A 22-nm SRAM array was overstressed with a series of gradually increasing voltage biases followed by EBIRCH scans at 1 V and 2-kV SEM imaging until fins were observed. It was found that the fins of a pulldown device could be imaged by EBIRCH at just 12 nA of shorting current, representative of a soft failure. Stressing the sample at higher voltages eventually created an ohmic short, which upon further investigation, strongly suggested that the Seebeck effect plays a significant role in EBIRCH analysis.

In this paper, we describe the difference between oscilloscope pulsing tests and waveform generator fast measurement unit (WGFMU) tests in analyzing high-resistance defects in DRAM main cells. Nanoprobe systems have various constraints in terms of pulsing whether it involves an oscilloscope or pulse generator. There are certain types of devices, such as DRAM cells, for which these systems are ineffective because saturation currents are too small. In this paper, we address this constraint and propose a new way to conduct pulsing tests using the WGFMU's arbitrary linear waveform generator in combination with an electro-optical nanoprobe.

In order to understand and communicate a PFA strategy during an analysis, a two-dimensional diagram of the layout of a suspect net has been developed. Net connections are extracted from the layout and drawn in a two-dimensional stitch diagram. The result is a simplified diagram providing a stack view of the layout layers for the net(s) of interest. Key analysis decisions are made and communicated using the stitch diagram. Using this diagram, selective nanoprobe measurements are made. Software implementation that extracts and draws the diagram allows for faster creation as well as making larger nets practical. As examples show, nanoprobe curve trace analysis using a simplified diagram has proven to be a successful evidence based approach to physical failure analysis of complex nets.

For advanced node semiconductor process development, manufacturing, fault isolation and product failure analysis, nanoprobing is an indispensable technology. As the process technology node scales, transistors and materials used are more susceptible to electron beam damage and changes. As scanning electron microscope (SEM) energy decreases to minimize electron beam damage, imaging resolution degrades. Process scaling has not only affected patterning dimensions and pitch scaling, but also materials utilized in advanced nodes. The material used at the contact level has changed from tungsten (W) to cobalt (Co), in combination with ultra-low K dielectrics. These new materials tend to make sample preparation and probing increasingly more challenging. At advanced nodes with sub-20nm contacts, probe landing accuracy and probe-contact stability are important to maintain good electrical contact throughout measurement time. In this paper, we discuss nanoprobing results from a 7nm SRAM obtained from a commercially available leading edge 7nm SOC.

The global radio frequency (RF) semiconductor market size is growing dramatically in recent years, especially with the growing demand for mobile devices, communication networks, automotive applications, etc. Failure analysis (FA) on RF devices is normally more complex than digital devices, especially when it involves soft failure. This paper discusses FA on an RF product soft failure issue by the pulsed currentvoltage (IV) nanoprobing technique. The device suffered from high-frequency failure and exhibited abnormal repetitive softstart signature. Previous publications on pulsed IV nanoprobing applications were mostly related to Front End Of Line (FEOL) issues and simulations. In most of these cases, the electrical abnormality could also be observed with normal DC IV measurement. In this paper, the pulsed IV nanoprobing was performed at the Back End Of Line (BEOL) interconnects to isolate the failure that was otherwise not detected with normal DC nanoprobing or the reported pulse IV measurement. The proposed method successfully isolate, simulate the failure, and helping us to identify the process and design rule weakness.

Nanoprobing systems have evolved to meet the challenges from recent innovations in the semiconductor manufacturing process. This is demonstrated through an exhibition of standard SRAM measurements on TSMC 7 nm FinFET technology. SEM based nanoprober is shown to meet or exceed the requirements for measuring 7nm technology and beyond. This paper discusses in detail of the best-known methods for nanoprobing on 7nm technology.

Non-volatile memory is the most important memory device in IC chips. As a memory, embedded non-volatile memory (NVM) is a fundamental structure in many kinds of semiconductor devices. It is commonly used in the modern electrical appliance as a code or data memory. For different applications, there are different memory designs or IP, like ROM, OTP, Flash, MRAM, PCRAM etc. The physical mechanism of these NVMs are different, some are electron based, some are resistance based and fuse or anti-fused based. The experiment described in this paper is performed on an electron charge storage based NVM. That means a medium is employed to store electron charge to differentiate two statuses “0” and “1”. Floating Poly gate is this medium used as electron charge storage in this NVM. Since the storage medium is in floating condition, it cannot be accessed externally. The methods of performing direct analysis are limited for this kind of device, especially in the case of subtle defects or soft fail. As semiconductor devices scale, the defects become smaller and more subtle. Nanoprobing is usually the only way to find the defect location electrically before any further physical analysis. In this experiment, the single bit NVM fail was analyzed. Different PFA methods used during the analysis, failed to find the defect. Nanoprobing was employed to precisely isolate the defect. Key word: nanoprobing, NVM, subtle defect, Poly-crystalline, floating gate

Reliability tests, such as Time-Dependent Dielectric Breakdown (TDDB), High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Those reliability tests are more stringent and complex especially for automotive Complementary Metal–Oxide–Semiconductor (CMOS) devices, this because it involves human lives and safety. In foundries failure analysis (FA), Transmission Electron Microscopy (TEM) analysis often required in order to provide insights into the defect mechanisms and the root cause of the reliability tests. In this paper, application of high resolution Nano-probing Electron Beam Absorbance Current (EBAC), Nano-probing active passive voltage contrast (APVC), and TEM with Energy Dispersive X-Ray Spectroscopy (EDX) to identify the failing root cause of Inter- Poly Oxide (IPO) TDDB failure on an automotive grade Non- Volatile Memory (NVM) device was investigated. We have successfully demonstrated that TEM analysis after Nanoprobing EBAC/APVC fault isolation is an effective technique to reveal the failure root cause of IPO breakdown after reliability stresses.

This paper presents Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) on a random time zero (t0) gate oxide defect within an IBM processor manufactured with a 14nm SOI (Silicon On Insulator) FinFET technology. The natures of the Functional Fail, the gate oxide defect, and the transistor characteristics are included. The impact of this gate oxide defect to product yield and performance, plus the extent to which it extends across the product chip, which includes passing circuits, is covered. Since chips, which may contain this defect, could be present within the entire product lifecycle, the reliability aspects of the defect at the transistor level were investigated. Among the various reliability stresses available for transistors, Constant Voltage Stress (CVS) Bias Temperature Instability (BTI) was chosen. CVS BTI stressing was able to be performed on both the NFETs and PFETs within the Inverter of the failing circuit, plus other identical reference circuits. The BTI stress nanoprobing is covered. This includes an overview of BTI stressing, confirming the nanoprobing system and electrical stress/test programs are adequate for BTI stressing, BTI stress methodologies for Inverters, plus the BTI stress results. The transistor level BTI stress results are discussed and compared to other published BTI literature. Finally, the reliability aspects of this gate oxide defect are discussed.

This paper demonstrates capacitance-voltage (CV) measurements using Nanoprobing to characterize different fails and better understand the defect mode. Three case studies are conducted using the CV technique. DC Nanoprobing measurements are first used to identify the failure mode. Subsequently, CV measurements are employed to further narrow down the root cause, to understand the process mechanism leading to the failure. A pathway to use the CV technique to isolate defects with-in a device under test is also demonstrated. It has been shown that the gate to lightly doped drain CV measurements will be a very useful characterization tool to understand various fail modes. This finding, along with DC measurement, serves to narrow the issue primarily to gate stack work function related matters.