In this paper, the stacking fault defects in FinFETs are described as the root cause of the PLL failure. Failure analysis approaches such as photon emission microscopy and nano probing were applied to pinpoint the exact stacking fault location in even transistor level and High resolution TEM confirmed the stacking fault defects in the Fin which was isolated by nano probing. RX local density was confirmed as the key factor in stacking fault generation by TCAD simulation. RX new mask with dummy addition was made to mitigate stress and was confirmed to be effective to reduce the compressive strain at the channel in FinFETs by Geometric Phase Analysis (GPA) which provided sufficiently practical local strain measurement data. The GPA techniques demonstrated here are informative for process improvement and failure analysis in FinFET devices. Keywords – Stacking Fault, Geometric Phase Analysis

This paper describes an electrical and physical failure analysis methodology leading to a unique defect called residual EG oxide (shortened to REGO); which manifested in 14nm SOI high performance FinFET technology. Theoretically a REGO defect can be present anywhere and on any multiple Fin transistor, or any type of device (low Vt, Regular Vt or High Vt). Because of the quantum nature of the FinFET and REGO occurrence being primarily limited to single Fins, this defect does not impact large transistors with multiple FINs; moreover, REGO was found to only impact 3 Fin or less transistors. Since REGO can be present on any multi-FIN transistor the potential does exist for the defect to escape test screening. Subsequently a reliability BTI (Bias Temperature Instability) stress experiment by nanoprobing at contact level was designed to assess REGO’s potential reliability impact. The BTI stress results indicate that the REGO defect would not result in any additional reliability or performance degradation beyond model expectations.

An application-specific integrated circuit (ASIC) for a high reliability application is found to have a missing sidewall spacer in a single transistor. Manufacturer burn-in and standard component electrical tests do not capture this defect. The defect manifests after exposure to ionizing radiation. Photon emission microscopy (PEM), laser voltage imaging (LVI), and laserassisted device alteration (LADA) are used to isolate the failure site. At the failure site a focused ion beam (FIB) cross section indicates that a doubly doped drain (DDD) (N+) is likely present where a lightly doped drain (LDD) is designated. This defect leads to a failure mode that is consistent with hot-carrier injection in complementary metal-oxide semiconductor (CMOS) transistors. This paper presents the testability from a fault isolation aspect, shmoo plot characterization, and backside optical techniques to identify its spatial location. A discussion of the results includes why ionizing radiation allowed the defect’s capture and potential implications of using ionizing radiation as a viable failure analysis technique.

Thermal issues management is a daily design challenge for teams working with analog mixed-signal technologies such as “SmartMOS”, with the integration of analog circuitry, high power density devices and logic control. A case study based on an NXP new product introduction will illustrate the use of Thermography as a complementary technique to standard Design debug activities, leading to the demonstration of a thermal crosstalk phenomenon in the analyzed analog mixed signal device. Based on InfraRed Thermography principle and specific Trigger Delay and Thermal Mapping modes, a transient thermal event was fully characterized, in addition to more common techniques such as Design and Layout study, electrical characterization, simulation, Microprobing, and Thermal Laser Stimulation. The added value of the thermography, as well as the limitations of the technique, will be discussed in that paper.

In this paper we introduce a physical analysis approach using focus ion beam (FIB) and scanning electron microscopy (SEM) to investigate a micro defective structure at active contact trench which caused a voltage breakdown of power device. In this case study, a lower probe current through FIB milling and a lower accelerating voltage in SEM imaging have been applied to identify the micro structure defect.

The increasing electrical design and physical complexity of semiconductor devices, especially in the analog and mixed signal (AMS) applications, directly influences the development and evolution of fault isolation techniques. One of these techniques is Dynamic Laser Stimulation (DLS) which is widely used in the industry for effective identification of subtle failure mechanisms and soft defects especially for AC signal-related failures [1, 2]. However, for analysis of some complex AMS IC failure modes, the tool’s standard setup may not always be compatible with the biasing requirements of the device. For example, the setup would typically require expensive and intricate test systems (i.e. Automatic test equipment (ATE), SCAN tester, etc.) to be interfaced with the DLS tool for the analysis to be feasible and successful [3, 4]. This paper presents simple and practical techniques to implement DLS without the need for an expensive test support system. These techniques were applied in three different FA cases involving AMS ICs with complex and temperature-dependent failure modes. The results of subsequent analysis indicated success in isolating the exact defect sites.

The degraded performance of a power MOSFET affects customer system reliability and consumer perceptions of quality. Building a reliable product and associated application specific lifetime models to predict the suitability of a power device for a given solution can enable competitive advantages, increased quality, enhanced performance and result in market share gains. This paper describes the methodology employed to configure an application specific reliability test, the failure rates and modes observed, the package modelling, and design improvements implemented. The validation of such relative to its original form and competitor products is discussed where we demonstrate a doubling in performance and an approximate 50% increase in current handling capability. This type of analysis and application specific approach to innovation enables one to focus design improvements in areas most relevant to customer concerns while at the same time adding credibility to specified product limits.

This paper shows that by combining electrical fault isolation and characterization by microprobing with physical fault isolation techniques both what is wrong with the circuit and where the defect is located can be determined with less microprobing and more safety from electrical recovery. In the first example, the unit was powered up using the optical beam induced resistance change (OBIRCH) supply, and OBIRCH was performed to determine if there were OBIRCH site differences between the good part and the return. The second example uses a combination of electrical fault isolation and characterization with microprobing and the physical fault isolation tool of lock in thermography (LIT). With these two examples, it has been shown that the use of electrical fault isolation and microprobing can be used to enhance the physical fault isolation tools of OBIRCH and LIT.

Photon Emission Microscopy (PEM) is one of the commonly used and powerful techniques for fault localization which uses a sensitive camera (like CCD or InGaAs) to detect a light (photon) emission from an electrically biased device. The fault localization of an open anomaly can be a challenge for the failure analysis. This paper discusses a novel technique for localization of an open fault on a thin-film resistor using induced photoemission method. In this proposed method, an emission site is induced at the open fault location on the thin-film resistor. This method was found to be effective and it increases the success rate for an open fault localization on a thin-film resistor.

As the Internet of Things, smart factories and autonomous driving increase the demand for low-price radar sensors, the authors address this need by developing a 24 GHz short range radar in standard bulk silicon CMOS technology for mass market production. CMOS technology enables cost reduction and efficient system integration compared to former GaAs and current SiGe solutions. Design for failure analysis (DFFA) is implemented in the low-noise amplifier (LNA) of the radar to identify and compensate process deviations. It consists of scalable capacitor structures and is executed using focused ion beam circuit edit. By doing so, the design specifications of high gain and low noise of the LNA are reliably met at high yield for the desired operating frequency. The presented DFFA method enables a shift in peak gain by 2.5 GHz. It thereby improves gain and noise figure at 24 GHz by 2 dB and -0.2 dB respectively. The resulting optimized LNA achieves a gain of 20 dB and a noise figure of 3.7 dB matching and surpassing other state-of-the-art works in a single prototyping run.

This paper provides an innovative root cause failure analysis method that combines multiple failure analysis (FA) techniques to narrow down and expose the shorting location and allow the material analysis of the shorting defect. It begins with a basic electrical testing to narrow down shorting metal layers, then utilizing mechanical lapping to expose over coat layers. This is followed by optical beam induced resistance change imaging to further narrow down the shorting location. Scanning electron microscopy and optical imaging are used together with focused ion beam milling to slice and view through the potential shorting area until the shorting defect is exposed. Finally, transmission electron microscopy (TEM) sample is prepared, and TEM analysis is carried out to pin point the root cause of the shorting. This method has been demonstrated successfully on Western Digital inter-metal layers shorting FA.

Photoluminescence, defect-band emission, and Lock-in Infrared Thermography (LIT) generally enable the correlation of multi-crystalline silicon defect types. Long Wavelength Infrared (LWIR) thermal imaging has traditionally seen limited application in failure analysis. LWIR cameras are typically uncooled systems using a microbolometer Focal Plane Arrays (FPA) commonly used in industrial IR applications, although cooled LWIR cameras using Mercury Cadmium Tellurium (MCT) detectors exists as well. On the contrary, the majority of the MWIR cameras require cooling, using either liquid nitrogen or a Stirling cycle cooler. Cooling to approximately −196 °C (77 K), offers excellent thermal resolution, but it may restrict the span of applications to controlled environments. Recent developments in LWIR uncooled and unstabilized micro-bolometer technology combined with microscopic IR lens design advancements are presented as an alternative solution for viable low-level leakage (LLL) defect localization and circuit characterization. The 30 micron pitch amorphous silicon type detector used in these analyses, rather than vanadium oxide (VOx), has sensitivity less than 50mK at 25C. Case studies reported demonstrate LWIR enhanced package-level and die-level defect localization contrasted with other quantum and thermal detectors in localization systems.