Secondary electrons potential contrast (SEPC) by scanning electron microscopy has emerged as a powerful tool for two-dimensional quantitative dopant imaging. The main component of the SEPC signal arises from the difference in the built-in potential between differently doped regions; which is very high in wide-band-gap semiconductors and particularly intense in SiC. This paper, after discussing the physical principles leading to the dopant contrast and the proper experimental setup, investigates the impact of relevant factors such as experimental conditions, surface effects, and sample preparation on image quality. The quantitative capabilities of this technique are demonstrated by the analysis of different test structures and prototypes of power devices such as MOSFET and JFET. The application to completely process devices demonstrates that SEPC represents an unequalled characterization technique, which provides accurate imaging and dopant profiling capabilities for silicon carbide devices.

Failure analysts occasionally find themselves faced with the problem of having one of the various defect isolation techniques indicating a defect location, and yet no defect is readily visible through the various imaging methods available. Many common conventional imaging tools, such as scanning electron microscopes (SEM), display images in shades of gray. The human eye is inherently more sensitive to changes in color rather than changes in grayscale. As a result, subtle variations in grayscale which could indicate the defect location can go unobserved unless a careful examination of the image intensities is performed. One useful way to highlight these variations is through intensity profiling where a line scan is drawn through the region under investigation and compared to an identical reference location contained within the same image. Subtle variations in the intensity profiles can then be identified and defect locations can be pinpointed to specific locations for later cross sectioning and final root cause determination. This paper discusses the application of this methodology to two case studies: a resistive short and a resistive open.

It is shown that a focused ion beam (FIB) grounding technique can be used to alleviate charge buildup on samples that would otherwise charge in the electron beam to the point where analysis by Auger electron spectroscopy (AES) was limited or impossible. FIB grounding alleviates the sample charging and permits AES analysis. The grounding technique is quick, easy and well understood as it has been used extensively for voltage-contrast analysis. The technique is shown to be useful for enabling analysis on electrically isolated conductive features as well as insulating samples.

In this paper the artifacts of additional copper signal induced by the copper grid, one of the most widely used supporting grid for focus ion beam (FIB) prepared TEM sample, is studied. Its influence on both the spot and the line scan energy dispersive spectroscopy (EDS) analyses are described. It was determined that, during line scan analysis, the strength of the copper signal varied between heavy and light elements, which could lead to inconclusive results during the EDS analysis of Cu interconnect structures. Based on the study using nickel support grid, it is concluded that the additional copper signal is a result of electrons scattered by the sample striking the Cu grid.

After wafer-die sawing process, sometimes silicon (Si) dust on microchip Al bondpads is difficult to be cleaned away by DI water, especially at pinhole/corrosive areas caused by galvanic corrosion, thus resulting in non-stick on pads (NSOP) problem in assembly process. To eliminate NSOP problem due to Si dust contamination, in this paper, we will study the mechanism of Si dust contamination and propose a concept of Si dust corrosion. A theoretical model will be introduced so as to explain Si dust contamination and corrosion problem during wafer die sawing process. Based on the mechanism proposed, Si dust contamination and corrosion is related to galvanic corrosion as OH- ions generated from galvanic corrosion will not only react with Al to cause Al corrosion, but also react with Si dust to cause Si dust corrosion. During Si dust corrosion, poly-H2SiO3 and Si-Al-O complex compounds will be formed on Al bondpads, especially at the pinholes/corrosive areas. Poly-H2SiO3 and Si-Al-O complex compounds are “gel-like” material and stick onto the surface of bondpads. It is insoluble in water and difficult to be cleaned away by DI water during or after wafer die sawing process and will cause bondpad discoloration or/and NSOP problem. Some eliminating methods of Si dust contamination and corrosion on Al bondpads during wafer die sawing process are also discussed.

SEM analysis of 193-nm photoresist profiles after cross section is seen to be critical because of the shrinkage of the photoresist material during electron beam exposure. With a combination of AFM and SEM investigations on AuPd sputter prepared samples an averaged shrinkage behaviour of height and width of resist lines of varying geometry can be quantitatively determined. This helps to a more accurate determination of resist line profiles.

This article presents a novel method to provide whole Deep Trench (DT) profile inspection. Bevel angle top-down polishing is used on pre-rotated substrates instead of traditional cross-section cleaving. This method can feedback the precise DT profile shape at specific depths to the production line for process tuning and troubleshooting.

The aggressive scaling of metal oxide semiconductor field effect transistor (MOSFET) device features, including gate dielectrics, silicides, and strained Si channels, presents unique metrology and characterization challenges to control electrical properties such as reliability and leakage current. This paper describes challenges faced in measuring the thickness of thin gate oxides and interfacial layers found in high-K gate dielectrics, determining Ni silicide phase in devices, and characterizing strain in MOSFETs with SiGe stressors. From case studies, it has been observed that thin layers (gate oxide, high-K film thickness, and interfacial layer) can be measured using high-resolution transmission electron microscopy (HRTEM) with good accuracy but there are some challenges in the form of sample thickness, damage-free samples, and precise sectioning of the sample for site-specific specimens. Complementary information based on HRTEM, annular dark field, and image simulation should be used to check the accuracy of thin gate dielectric measurements.

The demand for shifting from lead-containing to lead-free solder materials as well as the ongoing efforts for an improvement of the solder joint robustness for fine-pitch ball grid array packages requires ongoing testing of fresh solder alloys, changes in landing pad metallization and reflow processes. This testing includes mechanical and thermal stress tests and a detailed failure and material analysis. Besides the commonly used analysis methods like optical microscopy, scanning electron microscope (SEM) imaging of cross sections, fracture planes and energy dispersive X-ray compositional analyses, other techniques such as ion channeling contrast and transmission electron microscope (TEM) imaging can provide valuable information on intermetallic compounds (IMC) formation at solder joint interfaces. This paper discusses the advantages of SEM imaging of IMC morphology at the pad interface resulting from solder ball etching, focused ion beam imaging of solder ball cross sections with ion channeling contrast, and TEM analyses of failures.

In the field of semiconductor development and failure analysis, metrology of layers such as gate oxide layer is one of the important analysis due to determine semiconductor itself characteristics. The number of requirements of metrology is increasing by using both scanning and transmission electron microscopy. High accurate metrology depends on accuracy of magnification of electron microscope. We developed accurate magnification calibration for scanning transmission microscope. This method is carried out by using micro scale specimen and silicon single crystal lattice fringe images. We achieved absolute magnification error of less than 2% for all magnification. This microscope provides high accuracy metrology for semiconductor device. We describe an automatic magnification calibration function for the high magnification range required to accurately measure features from a few to tens of nm in size.

Advantages of low energy e-beam & i-beam in the operation and applications of SEM/FIB/EDS are presented. Further advantages of Backscattered Electron in SEM are stressed in the paper. However, since the “low energy” limit of zero is impractical, limiting factors and optimum operation conditions will be discussed. The article also investigates practical challenges associated with low energy beams in real situations.

In-line e-beam inspection is performed to detect dark voltage contrast (DVC) defects on normally bright W-plugs. Cross-sectional SEM and TEM in an FA lab verified that the different gray level values (GLV) of DVC defects are caused by different resistances of the W-plugs. We found that DVC defects with lower GLV (GLV1) are W-plugs that are open and almost open. DVC defects with GLV2 are caused by partially open W-plugs and in-plug voids.

The Directive 2002/95/EC (referred as ROHS) of the European Parliament and of the Council restricts the use of certain hazardous substances in electrical and electronic equipment. This article reports on a fast and inexpensive methodology for rapidly screening entire electronic assemblies that acts as a high-level screen for obvious ROHS violations. Using this methodology, this lab has been able to check entire product lines for basic ROHS compliance and has identified many cases where vendors needed to be informed of ROHS violations before a product could be certified as ROHS compliant. Four tests are employed. Each of them is described, along with the basic theory behind the test: pre-screening with x-ray fluorescence spectroscopy and electron dispersion spectroscopy; detection and identification of polybrominated biphenyl ethers using gas chromatography - mass spectrometry; and chromium 6 colorimetric testing based on diphenylcarbazide.

A stringent sampling plan is developed to monitor and improve the quality of 300mm SOI (silicon on insulator) starting wafers procured from the suppliers. The ultimate goal is to obtain the defect free wafers for device fabrication and increase yield and circuit performance of the semiconductor integrated circuits. This paper presents various characterization techniques for QC monitor and examples of the typical defects attributed to wafer manufacturing processes.

Interaction of inline SEM inspections with tungsten window-1 integrity were investigated. Multiple SEMs were utilized and various points in the processing were inspected. It was found that in certain circumstances inline SEM inspection induced increased window-1 contact resistance in both source/drain and gate contacts, up to and including electrical opens for the source/drain contacts.

The temperature and strain rate effects on the shear properties of selected Pb-free solders were investigated. The experiments were performed using single lap shear specimens. All testing was performed using a standard tensile test metrology. The following results were found: 1) Sn-3.5 wt.% Ag outperformed all the other solders in terms of its mechanical strength at all test conditions due to the formation of Ag3Sn precipitates in the bulk solder and Cu6Sn5 intermetallic formation along the interface. However, ductility was sacrificed as this solder strain hardens. 2) The strength and ductility of the solder joint is strongly dependent on the test temperature and strain rate. Data in this work reflects a decrease in strength and ductility when the test temperature is increased. This phenomenon can be attributed to the increase in energy as temperature is increased to overcome dislocation barriers such as impurities and grain boundaries that impede the motion of dislocation. When strain rate is increased, the amount of plastic deformation experienced by the solder increases and more dislocations are formed. Due to the increase in proximity and number of the dislocations, the net result is that motion of the dislocations are hindered thus requiring more stress to deform the material.

The identification of foreign material at metal-oxide interface or at the poly-substrate interface by means energy dispersive spectroscopy (EDS) is very difficult. Auger depth profiling can be used as an alternative method to cross-section EDS analysis for the identification of very thin layers of foreign material in semiconductor devices. This article presents a sample preparation method adapted from a planar transmission electron microscopy sample preparation method so that Auger depth profiling can be used as a practical tool for identifying very thin layers of foreign materials at interfaces buried deep within semiconductor devices. The discussion covers the advantages, applications, and the procedure for performing the analysis. The high degree of control provided by the method gives an analyst the ability to easily thin down material layers to less than 100nm of a target layer, thereby significantly reducing sample preparation time as well as analysis time on the Auger tool.

Ultra-thin (<100 nm) flakes shorting metal lines are difficult to detect and often cause the device to fail after reliability stress or at the customer site. In most cases, the common technique of inspecting the device in an optical microscope followed by conventional low energy (<3.0 kV) scanning electron microscopy (SEM) is often not able to detect this type of defect. In rare cases, where the defect is successfully exposed by the traditional procedure, it is very challenging to perform additional transmission electron microscopy (TEM) characterization of the defect without introducing arifacts during sample preparation of the exposed flake. A new procedure to identify these defects using a combination of face-lapping and high energy (>10 kV) SEM imaging is described in this paper. In this method, the failing device is carefully face-lapped and inspected frequently using a high energy (>10 kV) scanning electron beam. The high energy electron beam penetrates through the oxide layer and detects features embedded below the oxide. This technique greatly incresases the chances of detecting the flake, as the method is capable of detecting the defect at a larger range of oxide thickness as opposed to the traditional method. Additionally, TEM results were improved when the ultra-thin flakes were detected below the surface with the high energy SEM technique. Several examples of ultra-thin flakes found using the high energy SEM vs. low energy SEM will be presented.

In the selection of ultra low k materials, process compatibility is a very important factor. Plasma processing plays a critical role in enhanced interconnect integration. It is therefore important to study plasma interaction with the ultra low k materials and its effects on the structure and property of these materials. X-ray reflectivity (XRR) measurement can be used to measure film thickness, density and interface roughness, which are important parameters to check for after plasma treatments. In the current study, porous SiLK (p-SiLK) was treated with various plasmas, such as O2, O2/N2, H2/N2, CH2F2/Ar and CF4/O2. XRR results indicate that the density of the p-SiLK films remains unchanged after various plasma treatments. Surface roughening occurs during the plasma treatments, accompanied by the decrease in film thickness. Plasma-induced surface roughening was also observed using atomic force microscope (AFM). Such roughening is more severe for plasma treatments using oxygen-containing plasmas. FTIR analysis indicates that the chemical structure of the p-SiLK films is not significantly affected by plasma treatment. It is reasonable to conclude that oxidation of the surface plays a major role in the plasma-induced change in surface roughness and film thickness.

This paper describes a case study of a back end of the line low-k time dependent dielectric breakdown failure analysis. Due to the extremely large size of the stressed test structure, isolation of the defect and root cause determination can be quite difficult. In this particular study the defect was determined to lie in an approximately 100 um2 area and top down SEM inspection did not indicate any obvious defect. In an effort to further isolate the defect, an image comparison analysis was performed to highlight the differences between the fail area and an assumed good area of the test structure. A local area within the failing region was identified and imaged in cross section via TEM. The source of contamination which caused the fail was identified and appropriate process actions were implemented to remove the defect mechanism.