Redistribution layer (RDL) bonding pad over active circuitry is utilized to re-route the original bond pad to other location for wire bonding using RDL. The damages in the active circuitry beneath the RDL bond pad induced by stress from wire bonding and package must be evaluated for reliability in the product development. The experimental approach and test structures are proposed in this paper. Functional fail was detected in electrical test after reliability tests on packaged IC. The dielectric cracking initiated by wire bonding that corresponds to the functional fail is identified by physical failure analysis and Transmission-Electron-Microscopy (TEM) at a specific location beneath the RDL bond pad. Finite element simulations are used to analyze the wire bonding stress distribution and circuit-under-pad design effect. The predicted maximum stress for the dielectric cracking matches to the location observed in the physical failure analysis. Based on the experiment and the simulation data, design rules for the circuit routing beneath the RDL bond pad have been successfully developed that all product reliability tests pass later with extend bonding power. The results lead to significant improvements in the robustness of circuit routing structure beneath the RDL bond pad for dielectric cracking without modifications of the existing processes for the product.

Nanoprobing is one of the key characterization techniques for soft defect localization in SRAM. DC transistor performance metrics could be used to identify the root cause of the fail mode. One such case report where nanoprobing was applied to a wafer impacted by significant SRAM yield loss is presented in this paper where standard FIB cross-section on hard fail sites and top down delayered inspection did not reveal any obvious defects. The authors performed nanoprobing DC characterization measurements followed by capacitance-voltage (CV) measurements. Two probe CV measurement was then performed between the gate and drain of the device with source and bulk floating. The authors identified valuable process marginality at the gate to lightly doped drain overlap region. Physical characterization on an inline split wafer identified residual deposits on the BL contacts potentially blocking the implant. Enhanced cleans for resist removal was implemented as a fix for the fail mode.

A BEOL compatible Metal-Insulator-Metal capacitor (MIMCAP) was successfully developed for GlobalFoundries 14nm technology node, and subsequently introduced on customer designs as decoupling capacitors. The lead production silicon wafers with MIMCAP showed good functionality at wafer SORT functional test. However, upon testing more wafers, it became evident that the wafer center was impacted by abnormal scan logic fallout. The observed yield loss did not correlate with the MIMCAP scribe line Health Of Line (HOL) structures and the failure root cause could not be directly pin pointed to the MIMCAP process integration. Product scan diagnostic was performed and several systematic failing logical nets were identified. Subsequent failure analysis showed open via contacts in the MIMCAP vicinity. A detailed layout analysis of the FA confirmed weak-points and repeating logic nets allowed identifying a chip design topography issue resulting in a narrower process window compared to the scribe line MIMCAP HOL structure. Thanks to this knowledge the MIMCAP process was further optimized and the wafer center fallout was fully recovered in volume production.

With rapid scaling of semiconductor devices, new and more complicated challenges emerge as technology development progresses. In SRAM yield learning vehicles, it is becoming increasingly difficult to differentiate the voltage-sensitive SRAM yield loss from the expected hard bit-cells failures. It can only be accomplished by extensively leveraging yield, layout analysis and fault localization in sub-micron devices. In this paper, we describe the successful debugging of the yield gap observed between the High Density and the High Performance bit-cells. The SRAM yield loss is observed to be strongly modulated by different active sizing between two pull up (PU) bit-cells. Failure analysis focused at the weak point vicinity successfully identified abnormal poly edge profile with systematic High k Dielectric shorts. Tight active space on High Density cells led to limitation of complete trench gap-fill creating void filled with gate material. Thanks to this knowledge, the process was optimized with “Skip Active Atomic Level Oxide Deposition” step improving trench gap-fill margin.

Optical beam induced resistance change (OBIRCH) is a very well-adapted technique for static fault isolation in the semiconductor industry. Novel low current OBIRCH amplifier is used to facilitate safe test condition requirements for advanced nodes. This paper shows the differences between the earlier and novel generation OBIRCH amplifiers. Ring oscillator high standby leakage samples are analyzed using the novel generation amplifier. High signal to noise ratio at applied low bias and current levels on device under test are shown on various samples. Further, a metric to demonstrate the SNR to device performance is also discussed. OBIRCH analysis is performed on all the three samples for nanoprobing of, and physical characterization on, the leakage. The resulting spots were calibrated and classified. It is noted that the calibration metric can be successfully used for the first time to estimate the relative threshold voltage of individual transistors in advanced process nodes.

Low power mode current is a very important parameter of most microcontrollers. A non-production prototype microcontroller had high current issues with certain SRAM modules which were produced using a new memory compiler. All devices were measuring 100’s μA of low power mode current which was an order of magnitude higher than the requirement. Many failure analysis (FA) techniques had to be used to determine the root cause: Optical Beam Induced Resistance Change (OBIRCh), photo emission microscopy (PEM), microprobing, and nanoprobe device characterization. Transistor models and measurements of probe structures from the effected lots both predicted that the device low power mode current would meet expectations; however, all first silicon samples had elevated low power mode current. A knowledge of low power design methodology was needed to ensure all issues were discovered.

OBIRCH is a static technique for isolating both high and low resistance failures in test structures that continues to be relevant to sub 14nm technologies. While limited resolution is a factor as devices get smaller, an approximate location is adequate for finding obvious defects on sub 14nm technology structures. Its speed is what makes this technique appealing. If the approximate location isn’t good enough, a more time-consuming, higher-resolution technique can be employed. But the use of OBIRCH as a first isolation technique saves considerable time for a high volume FA lab if obvious defects cause the majority of failures. The seven case studies on sub 14nm technology are examples of obvious defects where OBIRCH had adequate resolution for isolation. The OBIRCH results for the first example are compared to the PVC (Passive Voltage Contrast) and EBAC (Electron-Beam Absorbed Current Imaging) findings to illustrate each technique’s strength and weakness.

Metal-insulator-metal (MIM) capacitors with single TiO2 and a TiO2/Y2O3 stack are used as insulator films in MIM and MEMS, respectively, are explored. It is found that, under electron injection from bottom electrode, the TiO2 MIM capacitors demonstrate resistive switching with a magnitude of leakage currents not usable for MEMS application. The deposition of a stacked TiO2/Y2O3 dielectric film improves the MEMS performance without compromising the low dielectric charging of TiO2 single layer.

This paper describes how a DDR loopback test failure was analyzed successfully after being repackaged from an MBGA into a TBGA package substrate. DDR loopback test methodology is discussed as well as the advanced failure analysis techniques that were used to identify the root cause of failure.

In a failure event, circuit schematic analysis usually follows after fault isolation to increase the success rate. However, analyzing an extracted netlist of the isolated sub-circuit can be messy. Manual circuit translation from layout where the analyst is in control of the cell instance placement is one way to overcome this challenge. Although it is neater and intuitive for analysis, it can be time consuming to create the schematic. To analyze circuits in a systematic manner, cross-mapping between layout and schematic contents is the most commonly recognized approach. However, at times, cross-mapping alone is insufficient and some further simplification procedures are favorable. This paper describes the challenges and illustrates using real case studies, how schematics re-ordering and substitutions can be useful to simplify and enhance circuit analysis. These procedures can be implemented in an automated manner to enhance turnaround time for analysis.

In this paper, the localization of open metal contact for 90nm node SOC is reported based on Electron Beam Absorbed Current (EBAC) technique and scan diagnosis for the first time. According to the detected excess carbon, silicon and oxygen signals obtained from X-ray energy dispersive spectroscopy (EDX), the failure was deemed to be caused by the incomplete removal of silicate photoresist polymer formed during the O2 plasma dry clean before copper plating. Based on this, we proposed to replace the dry clean with diluted HF clean prior to the copper plating, which can significantly remove the silicate polymers and increase the yield.

Failure analysis and defect localization on 28nm All Programmable Zynq System-on-Chip (SoC) device is extremely challenging. While conventional FPGA, which only consists of the Programmable Logic, has greater ease and flexibility in pattern generation during fault isolation, the all programmable SoC device integrates a dual ARM Cortex-A9 cores with Programmable Logic (PL) in a single chip. The cache data access in-between processor and PL is more complex and test methodology has lesser degree of control on cache data flow and stack sequence. This paper introduced an advanced fault isolation test methodology combining Software Development Kit (SDK) with scan based diagnostic test for cache failures. It successfully pinpoint to failure locations with physical defects found. As conventional physical failure analysis approaches using SEM based passive voltage contrast could not observe any abnormalities, current imaging and nano-probing measurement using AFP played critical roles in detecting nano-ampere leakages prior subsequent TEM analysis. The findings were then feedback to the foundry for process improvement. Furthermore, a new screening methodology is innovated where an extreme low-voltage test at high temperature in Automatic Test to detect and eliminate the process marginal leakage failure.

Soft failures are among the most challenging yield detractors. They typically show test parameter sensitive characteristics, which would pass under certain test conditions but fail under other conditions. Conductive-atomic force microscopy (CAFM) emerged as an ideal solution for soft failure analysis that can balance the time and thoroughness. By inserting CAFM into the soft failure analysis flow, success rate of such type of analysis can be significantly enhanced. In this paper, a logic chain soft failure and a SRAM local bitline soft failure are used as examples to illustrate how this failure analysis methodology provides a powerful and efficient solution for soft failure analysis.

With increasing complexity involved in advance node semiconductor process development, dependability on parametric test structures has also increased significantly. Test structures play a predominant role throughout the entire development cycle of a product. It becomes very important to understand the root cause of failures at fastest pace to take necessary corrective actions. The use of ultra low K dielectrics for back end of line wafer build for advanced nodes created significant constraints on conventional beam imaging methods for fault isolation. This paper provides a streamlined process flow for root cause identification on shorts on advanced 20 nm and sub-20 nm technologies. Three unique cases are presented to demonstrate three typical situations identified in the process flow. They are blown capacitors, gate leakage, and resistance ladder short isolation.

EBAC is a high-resolution, static technique that can be used for isolating electrical shorts, but it begins to fail for large, interconnected, test structures. In such cases, localization can be achieved when combined with optical localization techniques such as OBIRCH. This paper presents two case studies of subtle, FEOL shorts on a sub-14nm technology that required the resolution of EBAC.