E-beam Inspection (EBI) is used for in-line detection of defects in semiconductor manufacturing. This paper highlights a physical defect mode application where traditional defect inspection techniques, such as broadband plasma and dark field inspection were ineffective in finding the defects of interest. It describes the inspection setup and verification with failure analysis and the application of the technique. This inspection was implemented as a process monitor to detect excursions. The amount of process "ON" time after an etch-chamber part's change was identified as the main factor in MOAT defectivity. The correlation between EBI defect detection and leakage at in-line electrical test was further investigated by looking at each individual die and the leakage associated with the MOAT only. It was observed that the increased leakage could be due to another process factor in the process than a MOAT etch or a MOAT defect that was missed during the EBI inspection.

The accuracy of ion implantation is very important in semiconductor manufacturing and will directly affect the performance of the individual devices and even the whole chip. The deviations of ion implantation energy, dose and angle often result from abnormality of implant equipment or process design limit. The information of ion implantation energy, dose and angle can be qualitatively and quantitatively analyzed by SIMS (Secondary Ion Mass Spectrometry) [1], which provides a way to diagnose ion implanter issue. Based on SIMS analysis results, we can judge whether ion implanter meets the requirements and whether the process design achieves the expected goal. In this paper, we report a SIMS data analysis method determine the deviation of ion implantation angle. A term of deviation rate is defined and a related calculation method was introduced, which is proportional to the deviation angles of the ion implanter. Then, a statistical analysis on a large number of data of deviation rates and ion implantation angles showed that the sampling data followed normal distribution, and thus the corresponding 3 sigma could be obtained. Using the determined 3 sigma range of the deviation rates, we can define the acceptable range for deviation rate. Further, we can use the actual deviation rate to judge if the implant equipment needs maintenance or not, or suggest the direction for improvement. Finally, we set up an oriented and quantitative optimization method of angle deviation by the full mapping of SIMS depth profiles, which can directly set the relationship between the angle deviation and the adjustment parameters of ion implantation disk (Δ alpha, Δ beta). The equipment’s maintenance time and cost can thus be minimized. This method can be used as early detection to the abnormity of ion implant equipment.

A novel approach for the localization of weak points in thin transistor and capacitor oxides before electrical breakdown will be presented in this paper. The proposed approach utilizes Electron Beam Absorbed Current (EBAC) imaging based on Scanning Electron Microscopy (SEM). This technique uses the generation of additional charge carriers within the semiconductor substrate level by scanning with a focused electron beam. Over a thin transistor or capacitor oxide layer inside the interaction volume of the electron beam an increased tunnel current is visualized by EBAC and shows areas with different current intensities indicating weak points. These soft defect areas are investigated in comparison to references which were analyzed by using cross sectioning in a dual beam FIB/SEM system followed by a high resolution Transmission Electron Microscopy (TEM) investigation. The feasibility of this new technique is demonstrated on a defective transistor gate oxide test structure.

Aluminum-copper alloys are popular for many applications that take advantage of the combination of properties in the alloys. This paper describes the use of multiple advanced failure analysis tools to analyze the physical and chemical properties of Al-Cu alloy thin films.

The presence of crystalline defects, including dislocations and pipeline defect, is detrimental to both the processing and the intrinsic quality of semiconductor devices. The electrical parametric or functional failures generated by those defects require accurate identification and proper classification in a continuous improvement mindset. Depending on the failure analyst choice of the investigation technique, the distinction between a dislocation and a pipeline defect can be difficult. In this paper, based on case studies of mixed-mode devices, the various electrical and physical FA investigation techniques are explored and compared. From an electrical investigation standpoint, fault localization techniques will be reviewed (Thermal Laser Stimulation and Photon Emission Microscopy) as well as the direct electrical measurements means (external measurement and nanoprobing AFP). From a physical analysis standpoint, the use of various methods after deprocessing will be considered: top down delineation etch, Atomic Force Microscopy (AFM), Scanning Microwave Microscopy (SMM), and Transmission Electron Microscopy (TEM). The position of the defect as well as its physical signature observed through the various methods will determine its proper classification and will determine the appropriate corrective actions. The paper will be concluded with a discussion on the physical differences between a dislocation and a pipeline defect, as well as insights into the wafer fab manufacturing process.

An increasing number of foil capacitors (metallized thin film capacitors, MTFC) are used as filters in power converters. Thus, they are constantly connected between power lines (different phases) or between power lines and ground. However, after some years of operation, severe damage cases were observed, where filter capacitors became extremely hot and started a slow process of outgasing which sometimes is even ended by catastrophic burning. Failure analysis of surviving capacitors of the same kind in neighbor phases identified air inclusions as the cause, which led to internal corona discharge. Useful corona discharge measurements, based on a modification of the well-known partial-discharge (PD) tests, made it possible to assess capacitors on their potential risk of such failures. It turned out that many, even new foil capacitors, started internal corona discharge already underneath their official AC voltage specification.

In wafer fabrication, Fluorine (F) contamination may cause fluorine-induced corrosion and defects on microchip Aluminum (Al) bondpads, resulting in bondpad discoloration or non-stick on pads (NSOP). Auger Electron Spectroscopy (AES) is employed for measurements of the fluorine level on the Al bondpads. From a Process control limit and a specification limit perspective, it is necessary to establish a control limit to enable process monitor reasons. Control limits are typically lower than the specification limits which are related to bondpad quality. The bondpad quality affects the die bondability. This paper proposes a simulation method to determine the specification limit of Fluorine and a Shelf Lifetime Accelerated Test (SLAT) for process monitoring. Wafers with different F levels were selected to perform SLAT with high temperature and high relative humidity tests for a fixed duration to simulate a one year wafer storage condition. The results of these simulation results agree with published values. If the F level on bondpad surfaces was less than 6.0 atomic percent (at%), then no F induced corrosion on the bond pads was observed by AES. Similarly, if the F level on bond pad surfaces was higher than 6.0 atomic per cent (at%) then AES measured F induced corrosion was observed.

Ni(5 at.%Pt ) films were silicided at a temperature below 400 °C and at 550 °C. The two silicidation temperatures had produced different responses to the subsequent metal etch. Catastrophic removal of the silicide was seen with the low silicidation temperature, while the desired etch selectivity was achieved with the high silicidation temperature. The surface microstructures developed were characterized with TEM and Auger depth profiling. The data correlate with both silicidation temperatures and ultimately the difference in the response to the metal etch. With the high silicidation temperature, there existed a thin Si-oxide film that was close to the surface and embedded with particles which contain metals. This thin film is expected to contribute significantly to the desired etch selectivity. The formation of this layer is interpreted thermodynamically.

Test structure characterization plays a predominant role throughout the entire development cycle of a product. They are used to understand the process windows and also help to monitor the health of line (HOL). One of the key principles in successfully monitoring the HOL is to establish passing and failing electrical criteria to various test structures. This paper shows electrical and physical characterization of one such test structure. Further, a novel way of establishing electrical signatures to specific defect fail mode finger prints for early identification and monitoring of process-related defects is proposed.

In the context of the increasing complexity of materials used in semiconductor device processes, the STEM EDX technique is now used routinely. It can be used to discriminate stacked layers in advanced devices where STEM HAADF Z-contrast is not sufficient. Moreover, it allows a new use of planar preparation for layer investigation. The complexity of analyzed structures drives a need for 3D information which can also be obtained with the chemical information of the EDX analysis.

Transmission Electron Microscopy (TEM) and scanning TEM (STEM) is widely used to acquire ultra high resolution images in different research areas. For some applications, a single TEM/STEM image does not provide enough information for analysis. One example in VLSI circuit failure analysis is the tracking of long interconnection. The capability of creating a large map of high resolution images may enable significant progress in some tasks. However, stitching TEM/STEM images in semiconductor applications is difficult and existing tools are unable to provide usable stitching results for analysis. In this paper, a novel fully automated method for stitching TEM/STEM image mosaics is proposed. The proposed method allows one to reach a global optimal configuration of each image tile so that both missing and false-positive correspondences can be tolerated. The experiment results presented in this paper show that the proposed method is robust and performs well in very challenging situations.

Spectroscopic characterization of interconnects and circuits in semiconductor devices has become increasingly complicated as dimensions for breakthroughs and failure analysis are continuously shrinking. To achieve high spatial resolution infrared (IR) spectroscopic information, a pulsed infrared laser can be coupled to an atomic force microscope in the atomic force microscopy IR (AFM-IR) technique. The combination of AFM-IR and Lorentz contact resonance AFM (LCR-AFM) has great potential for providing high spatial resolution chemical and mechanical analysis. To demonstrate the feasibility of the AFM-based techniques, AFM-IR spectrum and images were obtained from the interlayer dielectrics of a test structure at a length scale shorter than the IR wavelength. Using the LCR-AFM technique, the relative mechanical properties of the components could be mapped distinctively by observing the contact resonance of the AFM probe. Finally, preliminary data suggest there may be AFM-IR spectral differences between contamination and the bulk material on a liquid crystal display.

Direct surface bonding of wafers in 3D integration requires perfectly smooth surfaces, with roughness values below 1 nm, usually characterized with Atomic Force Microscopy. An alternative technique, Digital Holography Microscopy is evaluated here and shown to be precise enough to differentiate adequate wafers, that is chemical mechanical polished, from non treated ones.

In this paper, a comprehensive analysis methodology for gate oxide integrity (GOI) failure using combined FA techniques is proposed. The current method integrates the failure analysis flow we previously reported with a new flow proposed in this paper. The method is applicable to a wide range of GOI failure cases and has been used in analyzing many product wafers with GOI failure. In particular, there is one wafer with GOI failure that results from known failed process machines. This wafer could be readily analyzed with this new method to identify the root causes. The newly proposed flow is based on our previous report on GOI failure analysis, but the detection limit of contamination elements was significantly improved. The enhancement of detection limit is mainly attributable to the utilization of Vapor Phase Decomposition and Inductively Coupled Plasma Mass Spectrometry (VPD ICP-MS). The ICP-MS technique is highly sensitive and capable of simultaneously measuring a large number of elements at very low concentration level in the range of ppb (part per billion) to ppt (part to trillion). This enhanced sensitivity enables effective investigation of contamination caused by specific machines. A case study of GOI failure investigated by the proposed new method will be discussed in detail. In the study, Al, Fe, Mo and Sn contamination from a suspected tool were detected by ICPMS, followed by confirmation by Secondary Ion Mass Spectrometry (SIMS) on the affected product wafers. Failurepart isolation investigations of the affected diffusion furnace revealed that the root cause of the failure is due to a defective gas flow valve.

The authors use electron spectroscopy for chemical analysis and Auger electron analysis to study the interaction of Cl and F with Al thin-films deposited as thin-films on Si wafers and as Al bondpads. The motivation behind the study is F contamination being the putative source of poor throughput at wafer probe. F species stemming from NH4F and XeF2 exposure behave quite differently from HF on the Al surface. Whereas HF tends to attack the Al metal and leave an extended oxygenated-fluorinated surface, NH4F and XeF2 promote the formation of a stable, non-deliquescent fluoride salt of aluminum. HCl is far less corrosive to Al than HF, leaving a thin chlorinated-oxygenated surface. Immersion of Al thin-films in tetra-methyl-ammonium hydroxide (TMAH) and NH4OH provided non-halogenated surfaces for comparison. With exposure to air, the surface coated with the fluorinated Al salt (NH4F) adsorbs oxygen from the air to form a segregated AlF3/Al2O3 bilayer that remains stable with a total thickness on the order of 5 nm to 10 nm. Furthermore, wafers treated with NH4F display stellar throughput performance at wafer test despite having surface F contamination. A mechanical rather than chemical model is proposed to explain the improved performance at wafer probe with the immersion of wafers in a bath containing fluoride salts before wafer probe.

In the manufacture of Printed Wiring Boards (PWB), unwelcome structures, such as nodules and whiskers can be formed during copper electroplating with copper sulfate. Copper (Cu) whiskers with lengths of up to a few hundred micrometers can lead to electrical shorts between layers or patterns. In this paper, we document factors that can affect the growth of Cu whiskers; decomposition of additives in the Cu electroplating solution, surface stress, acidic cleaner, and the ingredients of a dry film. Contaminants from outside of the electroplating bath and the ingredients of the dry film were shown as key components in the formation of Cu whiskers.

Scanning Spreading Resistance Microscopy electro-mechanical nanocontacts are nowadays well understood and numerous influent parameters have been identified (Bias, load, surface state of the sample, radius of curvature of the tip). Despite several simulation and modelization possibilities, calibration curves are required to ensure reliable electrical characterizations. In this paper, we bring, through nano-structural studies (Scanning Electron Microscopy, Transmission Electron Microscopy) of surface state of both SSRM tips and doped silicon surface a new understanding of tip-sample interaction during SSRM measurements. As a result of load, a nanometric residual amorphous silicon layer was observed which thickness depends on applied force and might be due to as well the plastic transformation (Si to β-tin phase) as plough-effect residues resulting from the tip indentation into the sample. It appears thus in a failure analysis process to find the best compromise between stable electrical SSRM response and sample/tip surface degradation.

Imaging tomography by transmission electron microscopy (TEM) is a technique which has been growing in popularity in recent years, yet it has not been widely applied to semiconductor defect studies and root cause determination [1- 3]. In part this is due to the complex equipment, computing needs, and microscope time required to generate the various images which ultimately compose the data set. However, the latest generation of TEMs—with their high level of stability and automation—are greatly reducing the resource needs to create high quality and informative movies of defects rotating about a central axis. One significant advance is the reduction in time required to fabricate a sample and perform the data acquisition by TEM. Today’s microscopes allow for sample fabrication to take place in a few hours or less and can acquire more than 100 images in about an hour at different sample tilt conditions with minimal analyst intervention. This paper describes using automated TEM sample preparation with dual beam focused ion beams (previously reported [4]) in conjunction with automated tomography software on a state-of-the-art TEM. By using an advanced tomography holder ±70° of tilt can be obtained. This is a powerful way to view defects as the failure can be viewed through more than 90° of rotation. Consequently a more complete understanding of the failure site can be obtained over a typical single projection TEM image. This can greatly facilitate root cause determination in a timely manner.

For 22nm technology node and beyond, fully depleted devices such as FinFET and ETSOI are leading candidates. Certain critical dimensions of such devices are well below 10nm, and only transmission electron microscopy (TEM) has the resolution to provide measurement with sub-nanometer accuracy. Due to the projection effect of TEM technique, comprehensive understanding of the 3D structure from 2D images is needed for process development of FinFET. This paper will address sample preparations and TEM imaging techniques for FinFET device at sub-100nm pitch.

Although the overall spatial resolution of backscattered electron (BSE) imaging suffers in comparison to secondary electron (SE) imaging, its superior sensitivity to atomic number (Z) contrast and ability to image through overlying insulation levels can provide a complementary approach for imaging subtle buried defects. BSE enables the localization and imaging of embedded defects through overlying insulator levels without the risk of compromising them with reactive ion etch (RIE) or plasma etch exposure or by anisotropic wet chemical delayering process steps. Once the embedded defect is localized with BSE in situ, subsequent imaging by cross sectional Transmission Electron Microscopy (XTEM) combined with elemental analysis by energy dispersive X-Ray analysis (EDX) or electron energy loss spectroscopy (EELs) can be performed without the risk of introducing artifacts. In this work, BSE imaging was successfully employed to image embedded subtle defects in 32nm node technologies through overlying insulator films not possible with conventional SE imaging techniques.