Focused Ion Beam (FIB) circuit edit allows for rapid prototyping of potential semiconductor design changes without the need to run a full manufacturing cycle in a semiconductor Fab. By FIB editing a completed module, thorough testing on the bench or in a full system can be achieved. Logic can be toggled, validation of speed enhancements performed, and constructive and destructive failure analysis can be enabled. In order to fulfill all the needs of clients in a rapidly evolving SOC driven market, simply modifying existing devices by “rewiring” circuits is becoming insufficient. Often the team is tasked with making very repeatable structures to aid the circuit analysis group. These include relatively precise resistors for tuning RF circuits (part of an RC network), adding known loads or delays, et cetera. Naturally resistive FIB deposited metal lines connected to the existing circuitry can be used in this capacity. FIB chip edit is considered to be a “Direct Write” process. The beam pattern in conjunction with process gases defines the regions of milling and deposition. Unfortunately, FIB edit is rarely an exact science. In many cases, a number of characteristics seem to be outside the realm of precise repeatable control. This is evident not only in individual tool operational logs but also in FIB tool matching, where maintaining identical system performance within the lab is difficult or nearly impossible. These characteristics are highly dependent on precursor reservoir composition and flow, surface adsorption conditions, beam patterning integrity, and the total interaction space of competing back sputtering during the new material structure formation. Due to these factors, the shape, composition and electrical performance of metal and insulator depositions vary over an often unacceptable range. As a result, we were not meeting the needs of some critical customer applications. Direct written precision resistive structures displayed several issues for which iterative edits were required to compensate for variability. When attempting to create an exact resistance, this process was not reliable, nor was it repeatable enough for accurate circuit performance trimming. Space-constrained serpentine resistors or multiple discrete resistors side-by-side showed the greatest process variability. Metal deposition processes tend to be somewhat self-limiting, so thick boxprofile lines are difficult to form. Conductive material deposited outside of the pattern definition (overspray) results in line-to-line leakages. Attempts to remove the overspray thru ion beam assisted etch-back tends to damage the deposited conductors and underlying insulators. The low-k region between lines can become cross-linked, experience gallium doping, and become tungsten impregnated. This lowered the resistivity of the insulator, increased the resistivity of the conductor, and produced variability in the device which was especially an issue when dealing with varying initial substrates. GLOBALFOUNDRIES began a project to create a more robust repeatable resistive structure by removing several variables. Rather than direct writing lines onto a top surface layer, a confined deposition based on the concepts of dual damascene processing used with copper layers in modern semiconductor fabrication will be employed. The damascene process begins with the definition of a box to be filled with a conductive material. The process of ion beam gas assisted anisotropic etching/milling has a far more predictable outcome than ion beam induced deposition. It is possible to create a surface box mill or even a deep drilled via of desired dimensions with a more consistent repeatability. Deposition of tungsten into a confined region using, for example, a W(CO)6 precursor and a Ga+ ion beam results in an excellent via fill. Using this behavior, precision resistors can be created with metal deposition within the trenches which are created by the gas assisted mill. An enclosed space can be filled nearly void-free, and has repeatable electrical parameters. The self-limiting factors with tungsten deposition go away as sputtered material becomes trapped within the well resulting in a near limitless Zheight potential. The constant dielectric with a uniform and contained tungsten fill can allow for a well-defined resistivity for the FIB deposited tungsten material. Having a known resistivity, calculation of dimensions for resistive and inductive structures during the design process becomes feasible. With process variability under control, structures can be formed reliably enough to offer this as a service to customers.

This paper describes the application of 3D FIB-SEM tomography as a method for quantifying process variations across the die and across the wafer, as well as layout investigations. In this study, the analysis of results acquired by 3D FIB-SEM tomography were applied to a 64L 3D-NAND device where process induced variation in the high aspect ratio vertical memory channels is measured and to a double stack 3D-NAND architecture, which is comprised of two 32-layer stacks where eccentricity of the pillars was evaluated for layers in both upper and lower stacks. In addition, a partial layout of a 14nm logic device is investigated by this method, demonstrating the capabilities for structural verification, and structural overlay of elements from a 7nm logic device were also evaluated. The results demonstrate the value of 3D FIB-SEM tomography for physical confirmation of the structural layout, which can be applied towards device debug and reverse engineering.

Secondary electron detector (SED) plays a vital role in a focused ion beam (FIB) system. A successful circuit edit requires a good effective detector. Novel approach is presented in this paper to improve the performance of such a detector, making circuit altering for the most advanced integrated circuit (IC) possible.

Dopants imaging using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy are used for identifying doped areas within a device, the latter being analyzed either in a top view or in a side view. This paper presents a sample preparation workflow based on focused ion beam (FIB) use. A discussion is then conducted to assess advantages of the method and factors to monitor vigilantly. Dealing with FIB machining, any sample preparation geometry can be achieved, as it is for transmission electron microscopy (TEM) sample preparation: cross-section, planar, or inverted TEM preparation. This may pave the way to novel SCM imaging opportunities. As FIB milling generates a parasitic gallium implanted layer, a mechanical polishing step is needed to clean the specimen prior to SCM imaging. Efforts can be conducted to reduce the thickness of this layer, by reducing the acceleration voltage of the incident gallium ions, to ease sample cleaning.

The ability to expose a huge kerf/PCM (Process Control Monitor) test structure at the same level is limited from top down finger polishing. Also, in Scanning Electron Microscopy (SEM) the electron beam (e-beam) shift for electron beam absorbed current (EBAC) analysis is not able to cover the whole structure. The recently implemented technique described herein combines the focus ion beam (FIB) chemical enhanced milling method with EBAC analysis to stop the polishing at the upper layer and split the EBAC analysis into portions from the test structure. These help to improve the area of interest (AOI) evenness and enable the extension of the EBAC analysis.

In the semiconductor chip manufacturing industry, a method of evaluating characteristics by applying a direct circuit edit at an already manufactured chip level is widely used in order to shorten the product development time and release the product to the market in a short time. [1] This is because, when the fab process is performed by modifying the mask to improve the characteristics as in the conventional method, it takes a lot of time and cost for feedback. Feedback of semiconductor characteristics through circuit edit can save 10-20 times in terms of cost and time. As the process becomes more complex and the pattern size becomes smaller, its benefits become even greater. However, when the chip level circuit edit is applied to the Chip Scale Package (CSP) IC, it is very difficult to apply a general method of the frontside circuit edit, so that the success rate of the circuit edit is lowered. In order to solve this problem, a circuit edit method in the backside direction of the chip has been attempted for many years. [2, 3] However, the backside circuit edit (BCE) has more difficulties than the frontside circuit edit. A typical issue is how to uniformly and precisely control and remove the backside Si of the circuit edit area. The following three points should be considered for this. First, the uniformity of the remaining silicon thickness should be high. Second, it is necessary to control the thickness of remaining silicon to an appropriate thickness in the process of removing backside silicon. Third, it is important not to damage the peripheral circuit during etching and deposition. In this paper, we propose a method to increase the backside circuit edit success rate of CSP IC using Al or Cu metal by controlling these three factors effectively.

The cross-sectional and planar analysis of current generation 3D device structures can be analyzed using a single Focused Ion Beam (FIB) mill. This is achieved using a diagonal milling technique that exposes a multilayer planar surface as well as the cross-section. this provides image data allowing for an efficient method to monitor the fabrication process and find device design errors. This process saves tremendous sample-to-data time, decreasing it from days to hours while still providing precise defect and structure data.