Abstract In this paper, we describe a silicon debug flow that uses debug-friendly scan test patterns to improve the efficiency of physical fault isolation of timing failures using time-resolved emission (TRE) system. Several techniques have been developed to generate the debug-friendly test patterns. We further show a silicon debug case of a 90nm design based on the proposed debug flow.

Abstract This paper presents an iterative diagnosis test generation framework to improve logic fault diagnosis resolution. Industrial examples are presented in this paper on how additional targeted pattern generation can be used to improve defect localization before physical failure analysis of a die. This enables failure analysts to be more effective by reducing the dependence on the more expensive physical fault isolation techniques.

Abstract This paper presents a deterministic diagnosis analysis method for hold-time faults in scan chains. The defects discussed in this paper are primarily seen at low Vdd values, so called Vdd-min defects; Vdd -max defects can also be a problem. Traditional approaches require data collection, the creation of additional patterns, and an iterative trip back to the tester. This is a time consuming process and does not always lead to a closed end solution. This paper also presents a method to detect multiple hold-time faults in the chain using auto generated pattern, real-time on the tester. The approach includes validation of the hold-time fault model, characterization of the failure behavior in terms of Vdd and data dependencies and finally localization to a cone of logic including the data paths and the clock trees. This method of hold-time localization is organized into three steps. First, the chain integrity test is run at the safe voltage. Second, a set of new patterns is created and run at the failing voltage. Finally, the data is shifted out and compared with the simulation result. The data provides the locations of all of the hold-time faults for the selected failing voltage. Combined with silicon voltage probing, the technique allows the analysis to localize the faults and to measure timing slack on sub-nets in the failing circuitry. This allows very close correlation between timing models and silicon performance leading to more robust design/process matching.