Dynamic Photon Emission Microscopy (D-PEM) is an established technique for isolating short and open failures, where photons emitted by transistors are collected by sensitive infra-red detectors while the device under test is electrically exercised with automated test equipment (ATE). Common tests, such as scan, use patterns that are generated through Automatic Test Pattern Generator (ATPG) in compressed mode. When these patterns are looped for D-PEM, it results in indeterministic states within cells during the load or unload sequences, making interpretation of emission challenging. Moreover, photons are emitted with lower probability and lesser energies for smaller technology nodes such as the FinFET. In this paper, we will discuss executing scan tests in manners that can be used to bring out emission which did not show up in conventional test loops.

Lock-in thermography (LIT), known as a powerful nondestructive fault localization technique, can also be used for microscopic failure analysis of integrated circuits (ICs). The dynamic characteristic of LIT in terms of measurement, imaging and sensitivity, is a distinct advantage compared to other thermal fault localization methods as well as other fault isolation techniques like emission microscopy. In this study, LIT is utilized for failure localization of units exhibiting functional failure. Results showed that LIT was able to point defects with emissions in the mid-wave infra-red (MWIR) range that Photo Emission Microscopy (PEM) with near infrared (NIR) to short- wave infra-red (SWIR) detection wavelength sensitivity cannot to detect.

Laser-based dynamic analysis has become a very important tool for analyzing advanced process technology and complex circuit design. Thus, many good reference papers discuss high resolution, high sensitivity, and useful applications. However, proper interpretation of the measurement is important as well to understand the failure behavior and find the root cause. This paper demonstrates this importance by describing two insightful case studies with unique observations from laser voltage imaging/laser voltage probing (LVP), optical beam induced resistance change, and soft defect localization (SDL) analysis, which required an in-depth interpretation of the failure analysis (FA) results. The first case is a sawtooth LVP signal induced by a metal short. The second case, a mismatched result between an LVP and SDL analysis, is a good case of unusual LVP data induced by a very sensitive response to laser light. The two cases provide a good reference on how to properly explain FA results.

In modern-day semiconductor failure analysis (FA), the need for computer-aided design (CAD) has extended beyond the sole physical layout to a much larger scope of integrated circuit (IC) design data, such as the source schematic and netlist. Due to the improved accuracy of predicted failures reported by test and diagnosis tools, it has become virtually mandatory to correlate the potential failing schematic features (e.g., nets and instances) to their corresponding location on the physical-CAD layout and actual device under test (DUT). This paper covers the latest advancements of utilizing IC design schematics for fast and accurate fault localization; along with some of the most-effective methodologies for efficient root-cause analysis.

Static Random-Access Memory (SRAM) failure analysis (FA) is important during chip-level reliability evaluation and yield improvement. Single-bit, paired-bit, and quad-bit failures—whose defect should be at the failing bit-cell locations—can be directly sent for Physical Failure Analysis (PFA). For one or multiple row/column failures with too large of a suspected circuit area, more detailed fault isolation is required before PFA. Currently, Photon Emission Microscopy (PEM) is the most commonly used Electrical Failure Analysis (EFA) technique for this kind of fail [1]. Soft-Defect Localization / Dynamic Laser Stimulation (SDL/DLS) can also be applied on soft (Vmin) row/column fails for further isolation [2]. However, some failures do not have abnormal emission spots or DLS sensitivity and require different localization techniques. Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP) are widely established for logic EFA, [3] but require periodic activation via ATE which may not be possible using MBIST hardware and test-patterns optimized for fast production testing. This paper discusses the test setup challenges to enable LVI & LVP on SRAM fails and includes two case studies on <14 nm advanced process silicon.

In this paper the authors will discuss an application of Single Shot Logic (SSL) patterns used for further localizing IDDQ failures using ATPG constraints and targeted faults. This new method provides the analyst a possibility of performing circuit analysis using IDDQ measurement results as a pass/fail criterion rather than logic mismatches. Once a defective area was partially isolated through fault localization, SSL patterns were created to control individual internal node logic states in a deterministic way. IDDQ was measured at each SSL iteration where schematic analysis can further isolate the failure to a specific location. Two case studies will be discussed to show how this technique was used on actual failing units, with detailed explanation of the steps performed that led to a more precise determination of the fault location in the suspect cell.

The examination of partially deprocessed ICs for well imaging has been investigated. First it has been shown [1] that Ga+ FIB imaging can readily and strongly highlight the N-well / P-well boundary in an IC as shown again here. Second, a model which only considers secondary electron creation and scattering [2] is confirmed to be sufficient for understanding these imaging effects. Heavy Ga doping provides no marked change in PVC (passive voltage contrast). Then comparisons in the same field of view between optimized He+ and Ga+ imaging, has shown that He+ provides much greater PVC contrast when looking through deep oxide, and much better resolution on shallow surfaces. The quantitative model Stopping and Range of Ions in Matter (SRIM) [3] was consulted and confirmed these expectations for resolution and depth superiority of the He+ beam. According to the SRIM, there may even be less damage from the He+ beam. Yet these known effects of Ga+ damage has not prevented its widespread use in semiconductor FA and process monitoring. Thus, the use of GFIS (Gas field ion source) He+ beam for voltage contrast and junction imaging warrants further exploration.

We report on using the voltage-contrast mechanism of a scanning electron microscope to probe electrical waveforms on FinFET transistors that are located within active integrated circuits. The FinFET devices are accessed from the backside of the integrated circuit, enabling electrical activity on any transistor within a working device to be probed. We demonstrate gigahertz-bandwidth probing at 10-nm resolution using a stroboscopic pulsed electron source.

Electron-Beam Induced Resistance CHange (EBIRCH) is a technique that makes use of the electron beam of a scanning electron microscope for defect localization. The beam has an effect on the sample, and the resistance changes resulting from that effect are mapped in the system. This paper explores the beam-based nature of the technique and uses understanding from another beam-based technique, Optical Beam Induced Resistance CHange (OBIRCH), to propose a dominant mechanism. This mechanism may explain the widely different success rates between different types of samples observed after six month’s use of the technique for isolations on large health of line structures in a failure analysis lab.

Bitmapping based on memory built-in self-test is the most efficient method to locate embedded memory defects in system-on-chips. Although this is the preferred approach to memory yield improvement, the procedure to enable bitmapping can be both time and resource-consuming. Therefore, it is not supported on chips that are not produced in high volume due to the low return on investment. EeLADA was explored as an alternative. Although its feasibility has been proven in a previous report, the localization capability or diagnostic resolution is limited to at best failing bit-lines. This work enhances this technique to achieve a resolution down to bit-cell level with an accuracy of less than 5 µm.

This paper describes a novel flow using analog simulations for the failure analysis of digital, analog, and mixed signal devices. Although cell level diagnosis tools are available in the industry, it presents a solution through analog intra-cell simulation particularly advantageous when multiple defects give the same fault result at cell level. Details of case studies such as the one analog intracell simulation on digital device and the analog laser voltage probing are covered. The aim of the simulation solution proposed is to support the failure analyst to interpret emission images on analog devices. The presented analog simulation flow consists of computing the current (or current density) in MOS and bipolar transistors and simulating the internal waveforms in digital or analog cells. It enables failure analysts to interpret light emission and laser voltage probing results obtained on a physical device in a fast and efficient way.

We report the results of our studies on thermally induced surface topography changes in ultra-thinned silicon flip-chip packaged devices. Previous results showed that over polishing can result in bump topography on the ultra-thinned Si backside. The topographic bumps were found to form over the solder bump locations on the die. Our latest results show that heating exacerbates the topological variation, possibly due to underfill shrinkage caused by additional curing during heating, or plastic deformation caused by underfill and bump CTE mismatch. Our findings are relevant for Visible Light Probing because the induced topography can prevent Solid Immersion Lenses from making the intimate contact necessary for optimum performance.

A recently developed technique known as Electron Beam Induced Resistance Change (EBIRCH) equipped with a scanning electron microscope (SEM) utilizes a constant electron beam (e-beam) voltage across or current through the defect of interest and amplifies its resistance variation. In this study, EBIRCH is applied for a 3D NAND structure device fault isolation but suffered from nearby dielectric film deformation. The characterization of such dielectric deformation and the possible mechanisms of e-beam induced damage are discussed. As well, a threshold condition to avoid from triggering the occurrence of dielectric damage is presented for shallow defect analysis in EBIRCH application.

Thermal-Laser Signal Injection Microscopy (T-LSIM) is a widely used fault isolation technique. Although there are several T-LSIM systems on the market, each is limited in terms of the voltage and current it can produce. In this paper, the authors explain how they incorporated an Amplified External Isolated Source-Sense (AxISS) unit into their T-LSIM platform, increasing its current sourcing capability and voltage biasing range. They also provide examples highlighting the types of faults and failures that the modified system can detect.

The work presented here is related to the utilization of computer aided design (CAD) Navigation tools in combination with images from Emission Microscope (EMMI) to improve the accuracy and efficiency of Failure Analysis. The paper presents the flow to quickly identify the failing device by taking the photon emission microscope image and CAD data as input. EMMI is used extensively for detecting leakage current resulting from device defects, e.g., gate oxide defects/ leakage, latch-up, electrostatic discharge (ESD) failure, junction leakage, etc. This emitted light is captured as hotspots on the image. A typical photon emission microscope image has a series of photon emission spots initiated by one physical defect. Not all emission spots may be defects; for example, emissions are shown during normal saturation or switching mode of the transistor. This results in multiple connectivity path between these spots which failure analysis (FA) engineer may want to analyze. The FA engineer wants to detect the one failed device which causes multiple other devices to show false hotspots. The work presented in this paper involves identifying all the devices beneath the hotspot areas, processing the connectivity of the found devices and extracting the schematic for all the devices beneath these hotspots. The connectivity between the devices could be direct connections through nets or indirect through “transmission gates”. The extracted schematic helps the FA engineer focus the FA work on critical devices such as a driver and enables faster and more accurate fault localization. The work in the paper shows the extraction of critical path of devices and their connectivity.

Previous study on the invasiveness of the CW 1340 nm laser source used in failure analysis, pinpointed silicide diffusions issue and experimentally defined a safe experimental area. In this paper the area of interaction between the laser and the device has been measured more finely by frequency mapping. Then a simulation is used to predict the threshold of degradation. To reinforce the correlation between the simulation and the experiments, we also make a comparison with the area defined in the previous study. Finally, we give the areas of interaction in function of the temperature and show how it can change in function of the device (geometry and metal layers).

Most modern system on-chip incorporates a significant amount of embedded memories to achieve a reduced power consumption, higher speed and lower cost. In general, such memories are evaluated using built-in self-testing methods and in the event of a failure, bitmapping is heavily relied on for fault localization to guide subsequent failure analysis. However, a fast yield ramp can be impeded when bitmapping is not enabled in time or is inaccurate. This work studies the feasibility of employing electrically-enhanced LADA as an alternative method to debug embedded memory failures. Results are presented to demonstrate that the resolution of localization depends on the precision of diagnostic test pattern used and the laser spot size.

During the last years, laser reflectance modulation measurements (i.e. LVI, CW-SIP etc.) have become indispensable tools for the analysis of logic circuits at frequencies in the megahertz range. In this paper we present a method to extend the usefulness of these methods to mixedsignal circuits driven at ultra-low frequencies in the kilohertz range. We show that by toggling the main power supply, information of the electric behavior can be easily obtained from analog structures, removing the need for tester-based stimulation. This method proved especially useful for the debugging of chip startup failures. We demonstrate this with two case studies. In a first case, a defect in the analog part shut down the digital part of the chip. This prevented the use of debugging methods such as the read-out of error registers or the use of scan chains. Conventional methods like photon emission microscopy and thermal laser stimulation were also not successful at finding the problem. However, laser-voltage imaging (LVI) of the analog circuit at key locations while toggling the chip power supply in the kilohertz range led us to the failing net. In a second case on a different product, we similarly identified a failing capacitor in the error logic by modulating the chip enable pin in the kilohertz range.

Dynamic Laser Stimulation using Continuous Wave (CW) Lasers has been a very important technique in fault isolating soft failures due to process defects and design speed paths in microprocessors. However, the rapid scaling down of the process technologies and the high density of logic laid out in silicon has made it difficult to precisely fault isolate using a conventional continuous wave laser which has a laser spot size of about ~300nm. Also, the remnant effects of a CW laser DLS like banding due to n-well interactions make it further difficult to achieve high resolution fault isolation. In this paper we discuss how by using a modulated pico-second pulsed laser, a DLS suspect is isolated to cell internal nets, which using a CW laser spanned across multiple cells. This is achieved by modulating the pulsed laser using an Electro-optical modulator and restricting the stimulation to only those parts of a test-pattern where the signal propagation occurs. Also, by synchronizing the pulsed laser with the clock of the test-program and changing the laser pulse delivery in time, high stimulation levels were achieved without being invasive. This revealed extra data points (DLS sites) that can help with making precisely accurate Physical FA plans that reduce turnaround time and also ensure high success rates. Specifically, in the case of a bridging defect between two nets wherein DLS sites were only seen on the victim net using conventional CW laser, the time resolved pulsed laser revealed DLS sites on the aggressor net as well. This confirmed the bridging between the two nets since the aggressor net was not electrically connected with the victim net. We discuss in detail how the DLS sites play their role in framing the perfect Physical FA plan. A detailed study of the resolution achieved using time resolved pulsed laser and its comparison with the same using a CW laser is shown on 14nm FinFET technology.

Visible light probing (VLP) introduced significant spatial resolution improvement by decreasing the wavelength beyond 1064nm. VLP requires thinning the device backside below 10micrometer. Once this challenge is addressed, questions arise regarding invasiveness: how does the laser affect the transistor performance, and how is this manifest in LVx (laser voltage imaging and laser voltage probing) measurements. This paper addresses these questions using a 785nm VLP system. The results are compared with those of 1320nm, 1154nm, and 1064nm when pertinent. It is concluded that changing wavelengths from the traditional 1320nm LVx laser to the visible 785nm laser provides a 40% resolution improvement. Fortunately, decreasing the incident 785nm power eliminates obvious signs of charge-carrier effects. Furthermore, the rise-time is not affected by the laser when measured from the gate.