The application of IR-Lock-In Thermography (IRLIT) has been extended from 2D and 3D package fault isolation to on-die level analysis. In addition, the technique has become more sensitive allowing for detection of much lower dissipated power. In this paper, several fault localization cases covering PCB assemblies down to die level analysis are discussed using IR-LIT and absolute temperature mapping. Where possible, the analysis is complemented with physical defect verification. The fault isolation cases include an ultra-low power dissipation (<150 nW) and several case studies with high ohmic connections. For the latter a new method based on phase mapping is discussed allowing for 2D localization of thermally invisible defects. The method will be demonstrated on a test vehicle where phase data extracted from a visible feature of the device under test is studied. After this, a case study at die level is presented in an attempt to distinguish the phase information from two stacked M2-M3 metallization layers of the Back-End Of the Line (BEOL). Finally, temperature mapping results of a 5 micron wide aluminum feature in silicon-oxide is presented that is pushing the optical resolution of the tool.

This research sets up failure analysis flow to verify failure mechanisms and root causes of different kinds of contact leakage. This flow mainly uses EBIC, C-AFM and nano-probing to do fault isolation and confirm electrical failure mechanisms. Appropriate sample preparation is also mandatory for FIB, SEM and TEM inspection.

Semiconductor devices are sensitive to contamination that can cause product defects and product rejects. There are many possible types and sources of contamination. Root cause resolution of the contamination source can improve yield. The purpose of contamination troubleshooting is to identify and eliminate major yield limiters. This requires the use of a variety of analytical techniques[1]. Most important, it requires an understanding of the principle of contamination troubleshooting and general knowledge of analytical tests. This paper describes a contamination troubleshooting approach with case studies as examples of its application.

With the development of semiconductor technology and the increment quantity of metal layers in past few years, backside EFA (Electrical Failure Analysis) technology has become the dominant method. In this paper, abnormally high Signal Noise Ratio (SNR) signal captured by Electro-Optical Probing (EOP)/Laser Voltage Probing (LVP) from backside is shown and the cause of these phenomena are studied. Based on the real case collection, two kinds of failure mode are summarized, and simulated experiments are performed. The results indicate that when a current path from power to ground is formed, the high SNR signal can be captured at the transistor which was on this current path. It is helpful of this consequence for FA to identify the failure mode by high SNR signal.

FIB/SEM and TEM are standard characterization techniques for evaluation of process modification of microelectronics samples. In this paper, artefacts from these techniques are studied. The sample preparation methods are optimized to avoid damages. Seal-ring structures are chosen as an example in this study to show artefacts and difficulties in SEM and TEM observations. Two cases of artefacts are considered: one with TEM sample preparation followed by TEM imaging, and the other one with SEM observations after FIB cross-sectioning. In the first case, electronic chips that failed during stress tests are investigated, while in the second case a part has been dismissed during robustness qualification test. In the former, thickness of TEM lamellae has been evidenced as a key factor for delamination between layers under beam, whereas in the latter, it was observed that the electron beam lead to a shrink of oxide layers, which induced the break of underlying contacts.

The advent of bare die form in the semiconductor industry driven by the high-performance multichip modules’ (MCM) requirement posed electrical access and testing challenges on customer returned units (CRUs) for failure analysis (FA). In this technical literature, the developed die extraction processes and re-packaging solution on molded MCM and flex package types were discussed.

Some of the most challenging task in analyzing fractures is a die that has not been fully cracked apart and a cracked die with electrical overstress damage. Traditional tools such as simple magnifying lens, optical microscope and up to the advance Scanning Electron Microscope are not enough to study the internal fractures or markings that could lead back to the origin of the crack. In order to study these internal fractures, the analyst tends to break the sample into pieces. However, this method creates additional mechanical stress and leads to a secondary crack where the point of origin will be difficult to analyze. This paper aims to introduce infrared microscopy in fractography (mainly on silicon) using cases and techniques to minimize the occurrence of secondary crack in analyzing internal fractures.

Given the challenges FA Engineers have in fault localization, top-side analysis is facing a major challenge with today’s advanced packaging and shrinking of die sizes. At wafer and die level it is relatively easy to probe with little or no sample preparation. Greater challenges occur after the die is packaged. The difficulty further lies in non-destructively analyzing the die. Another issue with failure analysis is accurately deprocessing the device for probe pad deposition. Techniques like Electro Optical Probing (EOP) or Laser Voltage Probing (LVP) acquire electrical signals on transistors and create an activity map of the circuitry. In failure analysis, it is applied to localize defects. This paper discusses integrating EOP techniques in traditional FA to localize failure in mixed signal ICs. Three case studies were presented in this paper to establish the technique to be effective, quick and easy to probe non-invasively with minimal backside sample preparation.

Scanning Acoustic Microscopy (SAM) is a very important tool in the evaluation of molded plastic electronic components. SAM is used to non-destructively determine the configuration and quality of components using ultrasonic sound waves and consequently is an important test step in the screening, Destructive Physical Analysis (DPA) or Failure Analysis (FA) of plastic components. SAM is performed in a water bath so if internal defects are open to the surface of the device they can fill with water and become invisible to SAM.

A case study is presented of a core CPU product where FA/FI debug is performed for an ESD-related pin leakage issue on an IO family to root cause and qualify the product. A Powered TIVA technique is used to localize the damage to the termination resistor circuitry of the affected IO block when the pin is tristated using a device tester. Failure characterization shows a gate to drain short on the transistor, with nanoprobing confirming a solid short on gate to drain and TEM finding a short at the location indicated by the TIVA hits.

Massively parallel test structures, based on looking for shorts between certain design elements in the SRAM cells, are becoming increasingly relied upon in yield characterization. The localization of electrical shorts in these structures has posed significant challenges in advanced technology nodes, due to the size, and design complexity. Several of the traditional methods (nanoprobing, OBIRCH, etc.) are shown to be inadequate to find defects in SRAM cells, either due to resolution, or time required. In recent years, the Electron Beam Induced Resistance Change (EBIRCH) technique has increasingly been utilized for failure analysis. Combining EBIRCH with other techniques, such as SEM based nanoprobing system and PVC, allows not only direct electrical characterization of suspicious bridging sites but also allows engineers to pinpoint the exact location of defects with SEM resolution. This paper will demonstrate the several cases where SRAM-like test structures provided extreme challenges, and EBIRCH was the key technique towards finding the fail. A node to node, node to wordline, and ground-ground contact fails are presented. A combination of EBIRCH with the more traditional techniques in advanced technology node is key to timely and accurate determination of shorting mechanisms in our test structures.

Many semiconductor products are manufactured with mature technologies involving the uses of aluminum (Al) lines and tungsten (W) vias. High resistances of the vias were sometimes observed only after electrical or thermal stress. A layer of Ti oxide was found on such a via. In the wafer processing, the post W chemical mechanical planarization (WCMP) cleaning left residual W oxide on the W plugs. Ti from the overlaying metal line spontaneously reduced the W oxide, through which Ti oxide formed. Compared with W oxide, the Ti oxide has a larger formation enthalpy, and the valence electrons of Ti are more tightly bound to the O ion cores. As a result, the Ti oxide is more resistive than the W oxide. Consequently, the die functioned well in the first test in the fab, but the via resistance increased significantly after a thermal stress, which led to device failure in the second test. The NH4OH concentration was therefore increased to more effectively remove residual W oxide, which solved the problem. The thermal stress had prevented the latent issue from becoming a more costly field failure.

As semiconductor technology keeps scaling down, plus new structures of transistor and new materials introduction, not only are new failure mechanisms introduced, but also old classic failure mechanisms get evolved. The obvious example of failure mechanism evolution is short defect. In the previous technologies, although short defects can happen in different layers and appear in different forms, they always happens at intra-level. As semiconductor technology advanced into nanometer regime, short defect no longer only happened in intra-level, but also more and more often happened in interlevel. Failure analysis on the inter-level short defects is much more challenging because they are usually due to interaction of two processes, such as process variation in two process steps at the same location, and often hide in the bottom of tapered and dense patterns. The conventional PFA (Physical Failure Analysis) methodology often misses discovering the defect and then the defect will be removed by subsequent polishing. This paper has demonstrated some methods to tackle the challenges with three case studies of such inter-level short defects in nanometer semiconductor technologies.

Efficient and effective failure analysis (FA) of low-resistive defect was studied by using layout-aware and volume diagnosis. Small or marginal defect is one of the most difficult defectivities to identify during FA effort, especially if defect-induced resistance is not as high as the electrical isolation can detect. Here, we used new analysis methodologies, particularly using layout-aware and volume diagnosis, and prioritizing patterns in terms of a defective risk for following FA. The actual FA work verified that new analysis methodologies successfully identified low-resistive defect of Back-End-of-Line (BEOL) which was not detected by a conventional way and efficiently reduced the turn-around time (TAT) of physical failure analysis (PFA) by 57%, prompting fast feedback to fab.

Reduced noise immunity due to dimensional shrinkage, lower operational voltages and increasing densities results in increased soft or random failures. In practice, noises are generated by complex operation of device. In Dynamic Random Access Memory (DRAM), failures by noise are regarded as either decrease in charge at cell capacitor or increase in systematic interferences. Simple equivalent circuit of One Transistor One Capacitor (1T1C) DRAM and theoretical approach in time-domain are provided for quantitative noise analysis related to sense amplifier circuitries. Results show that local voltage fluctuation reduces sensing margin to judge data-0 or data-1. This phenomenon is easily observed at 1T1C with high resistance because response of voltage generator is comparatively slow.

The advent of lock-in thermal imaging application on semiconductor failure analysis added capability to localize failures through thermal activity (emission) of the die. When coupled with creative electrical set-up and material preparations, lock-in thermography (LIT) [1, 2] application gives more possibility in exploring the failure of the device using low power settings. This gives higher probability of preserving the defect which leads to a more conclusive root cause determination.

As research in superconducting electronics matures, it is necessary to have failure analysis techniques to identify parameters that impact yield and failure modes in the fabricated product. However, there has been significant skepticism regarding the ability of laser-based failure analysis techniques to detect defects at room temperature in superconducting electronics designed to operate at cryogenic temperatures. In this paper, we describe preliminary data showing the use of Thermally Induced Voltage Alteration (TIVA) [1] at ambient temperature to locate defects in known defective circuits fabricated using state-of-the-art techniques for superconducting electronics.

Through inline processing of a prospective Spin on Hardmask (SOH) material, bubble defects were observed randomly across a wafer. Several complementary FA techniques were utilized to characterize the bubble defects including SEM, TEM, and chemical analysis techniques. The root cause of defect formation was identified as a raw material imperfection in SOH, which led to excessive outgassing. Imperfections within the substrate formed nucleation sites for outgassing of SOH material forming bubbles, which allowed voids to propagate. These findings led to implementation of greater quality control methods by the raw material manufacturer.

In recent years, laser reflectance modulation measurements are widely used in failure analysis. Among them, EOFM (Electron-Optical Frequency Mapping) technique is easy to operate and very practical. In this article, some images with abnormal EOFM phenomena and their corresponding defects are showing up, the causes of those abnormal EOFM phenomena are also pointed out. They prove that EOFM function is very effective for discovering open or high-impedance defects on metal trace and pinpointing short-circuit defects. In addition to the two aspects above, there are also some abnormal EOFM phenomena we couldn’t explain perfectly. We studied one of them and proposed two possible causes of the anomaly. After simulation experiment and calculation, it could be basically determined that the abnormal EOFM phenomenon was caused by the substrate noise current.

Different failure modes on a microcontroller-based SoC are presented. Several steps in the analysis needed to find the failure mechanism as well as prove "non-fails" amidst the maze of false positives and false trails, second-order effects, confusion and other challenges due to product complexity and the device's interaction with the embedded firmware (FW) are also discussed. The cases presented in this paper tackle issues that are related to FW, non-volatile memory (NVM), digital logic and analog modules.