Semiconductor devices are decreasing in dimensions and currently comprise stacks of ultrathin layers as in a spin-transfer torque magnetoresistive random-access memory (STTMRAM) device. For successful characterization by transmission electron microscopy (TEM) for failure analysis and device development, an accurate and controllable thinning of TEM specimens for is desirable. In this work, we combine plan view Ga focused ion beam (FIB) and post-FIB Ar milling preparation to prepare TEM specimens from a STT-MRAM device. Post-FIB Ar milling technique as a final polishing step of plan view TEM specimens was shown to prevent exposure of the tunnel barrier layer that can be damaged by the Ga FIB beam. We discuss the plan view FIB preparation, post-FIB Ar milling step and image analysis of the TEM images.

Moore’s law has been a major driving force in the development of novel semiconductor devices and has continued to hold its relevance over the years. The resultant, smaller and more powerful, microprocessors not only cater to the ever-increasing demands of the existing needs but also are important enablers of novel applications and discoveries in different areas. Several critical features of these latest devices are in the atomic to nanometer scale, which has enhanced the necessity of a largescale transmission electron microscopy (TEM) imaging-based metrology and failure analysis for their process development. As a result, the automation of lamella preparation using focused ion beam (FIB) and TEM imaging has gathered an enormous momentum in last few years. A key aspect of automating a large-scale TEM sample preparation not only involves the calibration of a given FIB tool to achieve an acceptable and repeatable quality of TEM samples but also to ensure that sample quality is consistent across the entire fleet of toolsets. In this work, the performance of three ThermoFisher Exsolve toolsets using a common tool calibration method for both, lamella thickness and targeting, has been compared. It was found that in general, thickness of TEM lamella showed a larger variation as compared to targeting over the period of one month. Lamella thickness showed a decreasing trend, and it entailed a need of recalibrating the tools in an interval of two weeks so that the variation in both thickness and targeting for the fleet can be kept within the desired specifications of ±3 nm (2σ).

Nowadays, semiconductor components are widely used in home electronic appliances, vehicles, industrial motor controls and beyond. The performance and reliability of these components are becoming more crucial and critical. Generally, a semiconductor component consists of lead frames, wires, dies and die attaches. Within the die, the die backside metallization, also known as “BSM,” plays an important role in electronic component manufacturing. The BSM is a layer that promotes good adhesion, electrical properties and long-term stability as a conductive pathway to the circuits. As such, the inspection on BSM is needed to ensure robustness. Several conventional methods have been developed to analyze the die backside metallization. In this paper, we will discuss the inspection on backside metallization and comparison among five sample preparation methods: mechanical cross section with ion milling, mechanical cross section with FIB cleaning, die frontside decapsulation with FIB cut from die surface and FIB cut from die sidewall, and component frontside lapping with FIB from the remaining silicon. Result comparison will be discussed in case studies and the advantages and disadvantages of the five methods will be compared.

In this work we present a new approach in physical failure analysis. Fault isolation can be done using volume diagnosis techniques. But when studying the identified defect sites by Focused Ion Beam (FIB) cross-sectioning, correct interpretation of the cross-sectional views strongly relies on choosing an appropriate cutting strategy. However, volume diagnosis techniques do not provide any information on which cutting directions and settings to choose to avoid misinterpretation of the spatial evolution of the defects. The proposed approach is to acquire FIB-SEM tomographic datasets at the defect sites to unequivocally characterize the defects in three-dimensional visualizations, independent of particular cross-sectioning strategies. In this specific case we have applied the methodology at a microcontroller for automotive applications on which a couple of floating VIAS were found. Thanks to the complete information obtained with the tomography, the defect could be assigned to a specific class of etching tools, and the root cause thus be solved.

Automated TEM lamella preparation using the remote CAD to SEM image alignment has been demonstrated for high volume failure analysis. The proposed method not only provides a secure means of using CAD design data during the lamella prep process, but offers an improved flexibility compared to conventional methods of processing CAD design file in a tool environment. The experiment showed that the new method is 3.1 times higher in throughput and requires 74 times less manhours, compared to manual process.

Complex failure analysis often requires the use of multiple characterization instruments. For example, a defect or failure may be localized using one tool, whereas the subsequent marking, precision targeting, and high-resolution analysis may require completely different instruments. As a result, the analysis workflows require sample and operator coordination between instruments and engineers, which leads to lower throughput and success rates. This paper describes a complete in-situ workflow for comprehensive failure analysis processes on a compound semiconductor using a state-of-the-art FIB/SEM system, incorporating electron channeling contrast imaging (ECCI) and a STEM-in-SEM detector used in unison with an insertable detector positioned underneath the sample to capture transmitted electron condensed beam electron diffraction (CBED) micrographs.

This study shows that a high-volume TEM workflow can be achieved for inline defect characterization by adding a defect marking step using commercially available tools. A simple user-assisted defect marking procedure added to a conventional automated ex-situ lift-out TEM workflow increased throughput by a factor of nearly three and reduced man-hours by an order of magnitude, a significant improvement over conventional TEM workflows.

The automation of TEM imaging and lamella preparation using focused ion beam (FIB) technology has gained significant momentum, particularly in the development of microprocessors. A key requirement of automating TEM sample preparation is ensuring consistent thickness control and accurate targeting of features of interest in the ultra-thin lamella. This work examines the factors that impact both metrics. It explains how FIB pattern calibration requires milling to be divided into steps to minimize the effects of drift, how the height of the protective cap on the ion-beam tip influences sample thickness, and how FIB aperture erosion has little impact on lamella thickness until it reaches a certain point where the lamella profile cannot be reliably maintained. It was also found that the tail of the ion beam remains invariant during aperture degradation in the operable range and that it plays a prominent role in determining the cross-sectional thickness of the TEM lamella.

This paper describes an accurate and controllable delayering process to target defects in new materials and device structures. The workflow is a three-step process consisting of bulk device delayering by broad Ar ion beam milling, followed by plan view specimen preparation using a focused ion beam, then site-specific delayering via concentrated Ar ion beam milling. The end result is a precisely delayered device without sample preparation-induced artifacts suitable for identifying defects during physical failure analysis.

This paper evaluates the use of plasma etching for preparing TEM specimens to analyze high aspect ratio 3D NAND integrated circuits. By controlling plasma etching parameters, a relatively high material removal rate could be obtained. Moreover, through the control of etch time, the top region of the test specimens could be completely removed down through the expected number of layers, making it possible to resolve details throughout the entire sample, particularly in the middle region of the 3D NAND, using TEM cross-section analysis.

This paper evaluates the use of nanomilling and STEM imaging to analyze failure mechanisms in sub-50 nm InP HEMTS. The devices were life tested at elevated temperatures and biases and their electrical characteristics were measured at each stress interval. Devices that were damaged were investigated further to assess the underlying failure mechanism. Advanced microscopy with sub-nm resolution was employed to examine the physical characteristics of the failed HEMT devices at the atomic scale. As the paper explains, the examination was conducted using a focused ion beam/scanning electron microscope (FIB/SEM), an Ar gas ion nanomill, and STEM imaging.

This paper explains how to localize metal-to-metal short failures in DRAM using mechanical grinding, plasma FIB delayering, and electron beam induced resistance change (EBIRCH) analysis. Experiments show that the slope created during grinding is compensated by PFIB delayering, producing a high-quality planar surface in the target layer and site. Target layers can thus be prepared at any location (site-free), likewise, defective areas can be delayered to any depth without damage (layer-free). After delayering, exposed surfaces are generally flat enough to allow an electron beam to evenly penetrate the device for precise EBIRCH analysis. With the use of more advanced device preparation methods, EBIRCH analysis has a higher chance of successfully localizing metal line/via shorts even in large regions that include the aluminum layer.