In this paper, we discuss and showcase a 2-step defect isolation methodology by combining Focused Ion Beam “circuit editing” (FIB circuit edit) and Passive Voltage Contrast (PVC) imaging. The combo technique is an effective, robust, and time saving method for isolating defects in large area circuit structures for advanced nodes. The application of FIB circuit edits successfully enhanced the PVC efficiency in defect isolation. More importantly, the developed 2-step methodology improves failure analysis (FA) success rate and quality, and reduces FA turn-aroundtime (TAT).

Circuit edit (CE) workflows are well established for FIB energies of 30kV and above. The small spot size associated with such energies provides good milling acuity and imaging resolution needed for advanced CE applications. However, with the introduction of FinFET transistors and decreasing technology nodes, the dramatic reduction in STI to gate distance reduction poses some challenges to circuit editing at these high energies. These include transistor performance degradation due to Ga+ implantation as well as significant lateral scattering beyond the Node Access Hole (NAH) as defined by the pattern. In addition, the relatively fast milling speeds may not give enough control to the user to endpoint at the appropriate layer. In this paper, a group of FinFET transistors on a special test chip was edited with the Ga beam at different energies. Transistor performances were then characterized to evaluate any degradation. The resulting characterization revealed how the transistor performance was affected by the injected ion beams and provided a guideline for the low-kV circuit edit workflow. A novel low-kV FIB workflow was proposed to minimize the transistor damage and maintain the IC functionality after the CE process. The workflow was applied to a challenging CE problem on a 5nm FinFET device. This task included step by step backside delayering at 5kV, preparing the sample for the final circuit edit operation at Metal-1. Working at low landing energies (e.g. 5kV) lowers subsurface damage and reduces etching speed, but with trade offs including lower image resolution, milling acuity, sputtering yield and signal to noise ratio (SNR). However, the consequences of these effects can be mitigated by use of appropriate chemistries with closed loop delivery control and extremely low beam currents (≤1pA), in concert with double aperture beam shaping to minimize beam tails. On the 5nm FinFET device, we demonstrate good delayering control by optimization of beam currents, and gas delivery on the Centrios HX circuit edit system from Thermo Scientific.

Reproducible laser-assisted metal deposition with copper hexafluoroacetylacetonate trimethylvinylsilane Cu(hfac) (TMVS) has been demonstrated on a range of relevant semiconductor insulating material surfaces including silicon dioxide (SiO 2 ), crystalline silicon (c-Si), and organic package material such as polyimide and printed circuit board (PCB) FR- 4. A key to reliable and chemically efficient growth is a novel copper chemistry delivery methodology using direct precursor pulsing. The laser power conditions for deposition are strongly correlated to the substrate material, with increased power for the more thermally conductive samples (0.8 – 1.0 W) and significantly less for packaging materials (50 mW). The laser-assisted copper growth results and material properties are comparable to the published literature. Examples of circuit modifications using this methodology demonstrate its valuable role in the future of circuit edit.

The workflow of backside IC circuit edits using low and high ion-beam energy is investigated. The imaging capabilities using a high keV beam are superior to that of lower beam energy, even when using low beam currents, on typical ion beam microscopes. In this work, we will test the parametric shift of IC components following the use of 5 keV Gallium Focused Ion Beam (FIB) to expose Shallow Trench Isolation (STI), depositing a protective dielectric layer, and then switching to 30 keV FIB to perform device alteration. Electrical testing results show that the devices exhibit only a minor parametric shift. We present a case study, performing circuit edit on a 7 nm process node using the proposed workflow. Finally, we discuss the advantages of the proposed workflow.

Modern processors rely heavily on memory arrays close to the logical processers to have minimal latencies and highest bandwidth for optimal performance. There are memory arrays in the client and server which are configured to different levels based on the size and latency required for the tasks. These memory arrays are separated into bit lines and word lines to address single bits and retrieve required data from the address of the memory location. In any new server validation, a memory access error can happen if the logical to physical memory address is not confirmed. This can lead to corrupt data and operation failure. We have employed here, novel targeted Focused Ion Beam (FIB) milling techniques for Logical to Physical (L2P) memory addressing validation and correction.

The characterization of back side illumination (BSI) image sensors is challenging because of the unique construction of such sensors with silicon on top. A novel method for BSI image sensor characterization is presented in this paper. The proposed approach is based on backside circuit editing using ion beam and optical imaging techniques. This provides access to buried conductors and creates probe points for measurements that can be made using an optical, electron beam, or mechanical micro/nano prober.

Focused Ion Beam (FIB) chip circuit editing is a well-established highly specialized laboratory technique for making direct changes to the functionality of integrated circuits. A precisely tuned and placed ion beam in conjunction with process gases selectively uncovers internal circuitry, create functional changes in devices or the copper wiring pattern, and reseals the chip surface. When executed within reasonable limits, the revised circuit logic functions essentially the same as if the changes were instead made to the photomasks used to fabricate the chip. The results of the intended revision, however, can be obtained weeks or months earlier than by a full fabrication run. Evaluating proposed changes through FIB modification rather than proceeding immediately to mask changes has become an integral part of the process for bringing advanced designs to market at many companies. The end product of the FIB process is the very essence of handcrafted prototyping. The efficacy of the FIB technique faces new challenges with every generation of fabrication process node advancement. Ever shrinking geometries and new material sets have always been a given as transistor size decreases and overall packing density increases. The biggest fundamental change in recent years was the introduction of the FinFET as a replacement for the venerable planar transistor. Point to point wiring change methodology has generally followed process scaling, but transistor deletions or modifications with the change to Fins require a somewhat different approach and much more careful control due to the drastic change in height and shape. We also had to take into consideration the importance of the 4 th terminal, the body-tie, that is often lost in backside editing. Some designs and FET technology can function acceptably well when individual devices are no longer connected to the bulk substrate or well, while others can suffer from profound shifts in performance. All this presents a challenge given that the primary beam technology improvements of the fully configured chip edit FIB has only evolved incrementally during the same time period. The gallium column system appears to be reaching its maximum potential. Further, as gallium is a p-type metal dopant, there are limitations to its use in close proximity to certain active semiconductor devices. Amorphous material formation and other damage mechanisms that extend beyond what can be seen visually when endpointing must also be taken into account [1]. Device switching performance and even transmission line characteristics of nearby wiring levels can be impacted by material structural changes from implantation cascades. Last year our lab participated in a design validation exercise in which we were asked to modify the drive of a multi-finger FinFET device structure to reduce its switching speed impact on a circuit. The original sized device pulled the next node in the chain too fast, resulting in a timing upset. Deleting whole structures and bridging over/around them is commonly done, but modifications to the physical size of an FET device is a rare request and generally not attempted. It requires a level of precision in beam control and post-edit treatment that can be difficult to execute cleanly. Once again during a complex edit task we considered the use of an alternate ion beam species such as neon, or reducing the beam energy (low kV) on the gallium tool. Unfortunately, we don’t yet have easy access to a versatile viable replacement column technology grafted to a fully configured edit station. And while there should be significantly reduced implant damage and transistor functional change when a gallium column FIB is operated at lower accelerating potential [2], the further loss of visual acuity due to the reduced secondary emission, especially when combined with ultra-low beam currents, made fast and accurate navigation near impossible. We instead chose the somewhat unconventional approach of using an ultra-low voltage electron beam to do much of the navigation and surface marking prior to making the final edits with the gallium ion beam in a dual-beam FIB tool. Once we had resolved how to accurately navigate to the transistors in question and expose half of the structure without disturbing the body-tie, we were able to execute the required cut to trim away 50% of the structure and reduce the effective drive. Several of the FIB modified units functioned per the design parameters of a smaller sized device, giving confidence to proceed with the revised mask set. To our surprise, the gallium beam performed commendably well in this most difficult task. While we still believe that an inert beam of similar characteristics would be preferable, this work indicates that gallium columns are still viable at the 14 nm FinFET node for even the most rigorous of editing requirements. It also showed that careful application of e-beam imaging on the exposed underside of FinFET devices could be performed without degrading or destroying them.

The characterization of Back Side Illumination (BSI) Image Sensor is challenging because of its unique construct with silicon on top. A novel approach for the BSI Image sensor characterization will be presented in this paper. The proposed approach utilizes the circuit editing through the silicon (backside) by ion beam and optical imaging. This technique allows access to the buried conductors and creates probe points for measurements, which are typically performed by an optical prober, electron beam prober or a mechanical micro/nano prober.

Fast and accurate examination from the bulk to the specific area of the defect in advanced semiconductor devices is critical in failure analysis. This work presents the use of Ar ion milling methods in combination with Ga focused ion beam (FIB) milling as a cutting-edge sample preparation technique from the bulk to specific areas by FIB lift-out without sample-preparation-induced artifacts. The result is an accurately delayered sample from which electron-transparent TEM specimens of less than 15 nm are obtained.

A protocol for obtaining an advanced TEM lamella geometry using FIB-SEM is presented. Lamella lift-out procedure might require multiple manipulation steps or even breaking the vacuum in order to reach inverted or plan-view lamella geometries. We have developed a setup which enables lamella transfer from a bulk sample onto a TEM grid within a single, very simple manipulation step, with no need to break the vacuum or unload the sample. Most importantly, this approach does not require any additional devices to be installed.

An advanced technique for site-specific Atom Probe Tomography (APT) is presented. An APT sample is prepared from a targeted semiconductor device (commercially available product based on 14nm finFET technology). Using orthogonal views of the sample in STEM while FIB milling, a viable APT sample is created with the tip of the sample positioned over the lightly-doped drain (LDD) region of a pre-defined PFET. The resulting APT sample has optimal geometry and minimal amorphization damage.

Focused Ion Beam sample preparation for electron microscopy often requires large volumes of material to be removed. Prior efforts to increase the rate of bulk material removal were mainly focused on increasing the primary ion beam current. Enhanced sputtering yield at glancing ion beam incidence is known, but has not found widespread use in practical applications. In this study, etching at glancing ion beam incidence was explored for its advantages in increasing the rate of bulk material removal. Anomalous enhancement of material removal was observed with single raster etching in along-the-slope direction with toward-FIB raster propagation at glancing ion beam incidence. Material removal was inhibited with raster propagation away from FIB. The effects of glancing angle and ion dose on depth of cut and volume of removed material were also recorded. We demonstrated that the combination of single-raster etching in along-the-slope direction by raster propagating toward-FIB at glancing incidence and a “staircase” type of etching strategy holds promise for reducing the process time for bulk material removal in FIB sample preparation applications.