This presentation covers ion beam analytical tools, their capabilities, and uses. It provides an overview of ion sources, examines emerging trends in surface analysis, and assesses the potential of ultrafast lasers for panoscopic patterning, athermal ablation, and elemental analysis. It compares and contrasts liquid metal, gas field, and plasma sources and presents examples highlighting the capabilities of FIB-SIMS and FIB-SEM Auger/XPS surface analysis techniques. It also introduces computationally guided microspectroscopy (CGM) and assesses its potential impact on multi-variant analysis, point spread deconvolution, and compressed sensing.

The step into the production line environment is a quantum leap for physical failure analysis (PFA) and will change its work in the near future. Wafer sacrifice for analysis becomes obsolete. The main benefits are: 1. reduction of wafer costs, 2. more splits per development lot, 3. reduced cycle time of analysis and technology development. Machines needed for that purpose are dual beam SEM/FIB tools. In the following we present solutions how PFA in a broad range can be carried out inside of a production line. The analyzed wafers can be fed back into the production flow which results in lower overall costs and the feedback loop to production engineers is dramatically shortened leading to reduced down times of production tools etc. The highest risk that has kept the majority of semiconductor manufacturers from proceeding into this direction is the contamination of the productive wafer with Ga, the FIB beam particle, that may diffuse into productive parts of the wafer during heat cycles after the analysis step. We show that the risk of contamination by Ga and other materials can be controlled.

The characteristics of an organic low-k dielectric during investigation by focused ion beam (FIB) are discussed for the different FIB application modes: cross-section imaging, specimen preparation for transmission electron microscopy, and via milling for device modification. It is shown that the material is more stable under the ion beam than under the electron beam in the scanning electron microscope (SEM) or in the transmission electron microscope (TEM). The milling of the material by H2O vapor assistance is strongly enhanced. Also by applying XeF2 etching an enhanced milling rate can be obtained so that both the polymer layer and the intermediate oxides can be etched in a single step.

Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.

Conventional focused ion beam (FIB) based specific area transmission electron microscopy (TEM) sample preparation techniques usually requires complex grinding and gluing steps before final FIB thinning of the sample to electron transparency (<0.25 μm). A novel technique known as lift-out, plucking or pullout method that eliminates all the pre-FIB sample preparation has been developed for specific area TEM sample preparation by several authors. The advantages of the lift-out procedure include reduced sample preparation time and possibility of specific area TEM sample preparation of most components of integrated circuit with almost no geometric or dimensional limitations. In this paper, details of liftout method, developed during the present work, for site specific x-sectional and a new site specific planar sample preparation are described. Various methodologies are discussed to maximize the success rate by optimizing the factors that affect the technique. In failure analysis, the geometric and dimensional flexibility offered by the lift-out technique can be used to prepare specific area TEM sample of back thinned die, small particles and packaged parts. Such novel applications of lift-out technique in failure analysis are discussed with the examples of TEM results obtained from GaAs and Si based devices. Importantly, it was possible to obtain high resolution lattice images from the lift-out samples transferred on holey carbon supported 3mm copper grids.

Device repair using Focused Ion Beam(FIB) systems has been in use for most of the last decade. Most of this has been done by people who have been essentially self-taught. The result has been a long learning curve to become proficient in device repair. Since a great deal of the problem is that documentation on this “art form” is found in papers from many different disciplines, this work attempts to summarize all of the available information under one title. The primary focus of FIB device repair is to ensure and maintain device integrity and subsequently retain market share while optimizing the use of the instrument, usually referred to as ‘beam time’. We describe and discuss several methods of optimizing beam time. First, beam time should be minimized while doing on chip navigation to reach the target areas. Several different approaches are discussed: dead reckoning, 3-point alignment, CAD-based navigation, and optical overlay. Second, after the repair areas are located and identified, the desired metal levels must be reached using a combination of beam currents and gas chemistries, and then filled up and strapped to make final connections. Third, cuts and cleanups must be performed as required for the final repair. We will discuss typical values of the beam currents required to maintain device integrity while concurrently optimizing repair time. Maintaining device integrity is difficult because of two potentially serious interactions of the FIB on the substrate: 1) since the beam consists of heavy metal ions (typically Gallium) the act of imaging the surface produces some physical damage; 2) the beam is positively charged and puts some charge into the substrate, making it necessary to use great care working in and around capacitors or active areas such as transistors, in order to avoid changing the threshold voltage of the devices. Strategies for minimizing potential damage and maximizing quality and throughput will be discussed.

Wide variations in the dose enhancement factor observed when milling silicon using Focused Ion Beam (FIB) XeF2 Gas Assisted Etching (GAE) prompted the development of a simple model of the GAE process. The model accounts for three material removal mechanisms: regular sputtering; gas-assisted sputtering; and spontaneous chemical reactions. An expression linking the dose enhancement factor, εd, to the gas and milling parameters has been derived. Experiments show that εd behaves as predicted; good quantitative agreement is achieved over wide ranges of milling parameters for εd values between 20X and 2500X. Conditions required to minimize variations in d and maximize material removal rates, M, are derived. It is shown that if the dose per unit area per raster is below a threshold value then εd and M depend only on the average current density J (the area of the box divided by the beam current). A consideration of the J regimes used for front-side and back-side FIB work shows why changes in εd have not previously been a problem but are inevitable when milling the large trenches characteristics of Flip Chip circuit modification work. While εd changes dramatically there is a region of J values for which M is approximately constant.

The reliability of FIB deposited Pt structures is assessed through lifetesting of product die and through stress testing of via-intensive test structures. Data is also presented for Pt resistance monitors collected over a 21 month period aimed at assessing the stability of the FIB deposition process. Two product types were subjected to HTOL and HTSS conditions at 125°C followed by temperature cycling. The test structures were stressed at different combinations of temperature ranging from 100°C to 140°C and with currents up to 5 mA. Neither product type experienced any FIB related failures whereas the test structure saw 70% fallout due to degradation of the Pt material within the vias. Temperature cycling did not precipitate any failures. The Pt resistance monitor data showed that film resistance increases with film thickness indicating the incorporation of organic byproducts from the deposition process.

We report on recent studies of the effects of 50 keV focused ion beam (FIB) exposure on MOS transistors. We demonstrate that the changes in transistor parameters (such as threshold voltage, Vt) are essentially the same for exposure to a Ga+ ion beam at 30 and 50 keV under the same exposure conditions. We characterize the effects of FIB exposure on test transistors fabricated in both 0.5 μm and 0.225 μm technologies from two different vendors. We report on the effectiveness of overlying metal layers in screening MOS transistors from FIB-induced damage and examine the importance of ion dose rate and the physical dimensions of the exposed area.

Dual beam FIBSEM systems invite the use of innovative techniques to localize IC fails both electrically and physically. For electrical localization, we present a quick and reliable in-situ FIBSEM technique to deposit probe pads with very low parasitic leakage (Ipara < 4E-11A at 3V). The probe pads were Pt, deposited with ion beam assistance, on top of highly insulating SiOx, deposited with electron beam assistance. The buried plate (n-Band), p-well, wordline and bitline of a failing and a good 0.2 μm technology DRAM single cell were contacted. Both cells shared the same wordline for direct comparison of cell characteristics. Through this technique we electrically isolated the fail to a single cell by detecting leakage between the polysilicon wordline gate and the cell diffusion. For physical localization, we present a completely in-situ FIBSEM technique that combines ion milling, XeF2 staining and SEM imaging. With this technique, the electrically isolated fail was found to be a hole in the gate oxide at the bad cell.

Both the increased complexity of integrated circuits, resulting in six or more levels of integration, and the increasing use of flip-chip packaging have driven the development of integrated circuit (IC) failure analysis tools that can be applied to the backside of the chip. Among these new approaches are focused ion beam (FIB) tools and processes for performing chip edits/repairs from the die backside. This paper describes the use of backside FIB for a failure analysis application rather than for chip repair. Specifically, we used FIB technology to prepare an IC for inspection of voided metal interconnects (“lines”) and vias. Conventional FIB milling was combined with a superenhanced gas assisted milling process that uses XeF2 for rapid removal of large volumes of bulk silicon. This combined approach allowed removal of the TiW underlayer from a large number of M1 lines simultaneously, enabling rapid localization and plan view imaging of voids in lines and vias with backscattered electron (BSE) imaging in a scanning electron microscope (SEM). Sequential cross sections of individual voided vias enabled us to develop a 3D reconstruction of these voids. This information clarified how the voids were formed, helping us identify the IC process steps that needed to be changed.

FIB Micromachining has long been an established technique, but until recently it has been overshadowed by the more mainstream semiconductor application of the Focused Ion Beam system. Nano- Structure fabrication using the FIB system has become more popular recently due to several factors. The need for sub-micron structures have grown significantly due to a need for enhanced optical and biological applications. Another reason for the growth in micromachining is the improvement made in the ability of FIB systems to produce geometric shapes with high precision. With the latest high-end FIB systems, it is possible to produce microstructures with tens of nano-meters of precision. Optical lens, AFM tips, and nano-apertures are all part of the growing application for FIB Micromachining. This paper will discuss the ability and limitations of the FIB system and some possible application for FIB Micromachining.

Focused Ion Beam is commonly used for IC repairs and modifications. However, FIB operation may also induce a damaging impact which can takes place far from the working area due to the charge-up phenomenon. A complete characterization joined to an in-depth understanding of the physical phenomena arising from FIB irradiation is therefore necessary to take into account spurious FIB induced effects and to enhance the success of FIB modifications. In this paper, we present the effects of FIB irradiation on the electrical DC performances of different electronic devices such as nMOS and pMOS transistors, CMOS inverters, PN junctions and bipolar transistors. From the observed behavior of the DC characteristics evolution of the devices, some suggestions about physical mechanisms inducing the electrical degradation are proposed.

Focused Ion Beam (FIB) is used to modify a ring-oscillator circuit to enable the direct characterization of AC hot-carrier effects. Probe access to internal device nodes is necessary to find out the amount of individual device degradation resulting from AC hot-carrier stress. The circuit modification on an existing wafer by FIB enables the direct measurement of individual device in the circuit before and after AC hotcarrier stressing without resorting to new mask sets and silicon wafer processing for new hotcarrier reliability test circuits that can provide realistic stress voltage waveform. Small pads produced by FIB have small acceptable impact on the stress waveform of the circuit and they still allow accurate measurement of the internal device nodes. FIB’s ‘cut and paste’ technique is used to form these probe pads. Some suggestions are made for the proper FIB work in this paper. The results of AC hot-carrier tests with the circuit modified by FIB are also presented with some illustrative figures.

The task of circuit repairing and debugging using a Focused-Ion-Beam system on multi-layered IC devices is often difficult and tedious, especially when desired or target metal nodes or layers are buried under other higher level or nontarget metal nodes or layers. As a result, not only are target nodes difficult to access, but also, undesired shorts are difficult to prevent. To further complicate the situation, as the number of metal layers increases, the lower level metal nodes become increasingly thinner, and the node population becomes increasingly denser. These conditions result in a decreased success rate utilizing the FIB and an increased turn-around time for design debugging. Besides significant improvement of the FIB equipment and tools, new techniques that can be used to overcome the difficulties encountered during FIB operations on multi-layered IC devices need to be utilized. In this paper, we will focus on discussion of some new techniques that can be used for FIB device modification work and device debugging on multi-layered IC devices, including C4 (controlled-collapse chip connection) flip-chip devices. Some recommendations and tips for using these techniques on complicated fib modification work will also be shared based on the author’s experience.

Focused Ion Beam (FIB) technique has been widely used to directly modify device functionality by adding ion-induced conductive lines and cutting signal traces with chemical enhance etching. However, in this work, FIB technique is employed to add a 15 ohm resistor to a RF circuit to solve its oscillation problem. After the modification, the oscillation problem is solved and the performance of the RF device is improved significantly. The successful FIB application of adding a defined resistor to modify a circuit is reported in this paper for the first time.

Recent planar technologies with 3 metal layers or more challenge current physical design modification capacities using Focused Ion Beam tools. Image visibility on the FIB is drastically reduced, making accurate positioning and milling operations in the area of interest more difficult, and the use of power planes increases the risk of short circuits while accessing inferior metal lines. Despite the complexity of FIB modifications, however, the demand for circuit modifications continues to increase. To respond to this demand for successful, time efficient, FIB modifications, step by step monitoring of operations is imperative. In this paper, we will present an innovative method which brings in-situ electrical monitoring and contactless measurement capabilities to FIB systems. Electrical connection of the circuit inside the vacuum FIB chamber is done using a commercial load module and logic waveform acquisition with the FIB is obtained without modifying FIB hardware using a voltage contrast approach. With this method, it is possible to verify the completion of FIB milling and depositing operations by temporarily suspending FIB action so that a test pattern can be run allowing electrical testing and measurements of the circuit without damaging it.

Copper will probably replace aluminum alloys as the interconnect metallurgy of choice for high performance semiconductor devices. This transition will challenge the suitability of established practices in focused ion beam (FIB) chip repair. A fundamental rethink in methodology, techniques, and process gases will be required to deal with the new metal films. This paper discusses the results of recent experiments in the areas of FIB exposure, cuts and connections to buried copper lines. While copper tends to mill faster than aluminum, etch rate variations due to grain structure tend to make reliable isolation cuts more difficult. The films also have been shown to suffer regrowth and surface reactions during long term storage following FIB exposure. Attempts at halogen gas assisted etch (GAE) mills result in undesirable removal characteristics, and in the case of bromine, the spontaneous destruction of all exposed copper in the immediate area. Resistance measurements and reliability of deposited tungsten connections to copper lines are also presented. In addition, the latest techniques developed for aluminum wiring isolation and device characterization are shown. These include 'cleanup' methods for achieving good circuit isolation without the extensive use of local oxide deposition, and the latest multilevel version of the FIB ‘wagon wheel’ for SRAM cell characterization. Also included is preliminary data from a custom built FIB chamber four manipulator prober module.

A selected area planar TEM (SAPTEM) sample preparation technique for failure analysis of integrated circuits using a transmission electron microscope has been developed. The technique employs a combination of mechanical grinding, selective wet/dry chemical etching (if required) and a two step focused ion beam IIFIB) milling. The mechanical grinding steps include: (a) a backside grind to achieve a die thickness less than 30 µm, (b) the support half ring glue, and (c) a cross-section grind from one side to reach less than 35 pm to the failing site. A selective wet or dry chemical etch is applied before, between,, or after FIB thinning depending on the nature of problem and device components. The FIB milling steps involve: (is) a high ion current cross-sectional cut to reach as close as 5-8 µm to the area of interest (b) a final planar thinning with the ion beam parallel to the surface of the die. The plan view procedure offers unique geometric advantage over the cross-section method for failure analysis of problems that are limited to silicon or certain layers of the device. Iln the cross-sectional approach, a thin section (thickness less than 250 µm) of a device is available for failure analysis, whereas in the planar procedure a 20 µm2 area of any layer (thickness less than 250 µm) of the device is available. The above advantage has been successfully exploited to identify and solve the following prablems in fast static random access memories (FSRAM): (i) random gateoxide rupture that resulted in single bit failures, (ii) random dislocations from the buried contact trenching that caused single bit failures and general silicon defectivity (e.g. implant damage and spacer edge defects), and (iii) interracial reactions.