We report on the development of a novel thermography technique, integrated Raman – IR thermography, illustrated here on AlGaN/GaN electronic devices. As it is a generic technique future application to Si, GaAs and other devices is anticipated. While IR thermography can provide fast temperature overviews, its current use for many of today’s technologies is complicated by the fact that it does not provide the spatial resolution needed to probe sub-micron/micron size active device areas. Integrating IR with micro-Raman thermography, providing temperature information with ~0.5 µm spatial resolution, enables unique thermal analysis of semiconductor devices to a level not possible before. This opens new opportunities for device performance and reliability optimization, and failure analysis of modern semiconductor technology, in research, development, and quality control / manufacturing environments.

Although RIL, SDL and LADA are slightly different, the main operating principle is the same and the theory for defect localization presented in this paper is applicable to all three methods. Throughout this paper the authors refer to LADA, as all experimental results in this paper were obtained with a 1064nm laser on defect free circuits. This paper first defines mathematically what 'signal strength' actually means in LADA and then demonstrates a statistical model of the LADA situation that explains the optimal conditions for signal collection and the parameters involved. The model is tested against experimental data and is also used to optimise the acquisition time. Through this model, equations were derived for the acquisition time needed to discern a LADA response from the background noise. The model offers a quantitative tool to estimate the feasibility of a given LADA measurement and a guide to optimising the required experimental set-up.

With shrinking feature size of integrated circuits traditional FA techniques like SEM inspection of top down delayered devices or cross sectioning often cannot determine the physical root cause. Inside SRAM blocks the aggressive design rules of transistor parameters can cause a local mismatch and therefore a soft fail of a single SRAM cell. This paper will present a new approach to identify a physical root cause with the help of nano probing and TCAD simulation to allow the wafer fab to implement countermeasures.

Due to relentless down scaling of device geometries, failure analysis is getting more and more complex. As a matter of fact, the success rate of Thermal Laser Stimulation (TLS) techniques drops significantly for 90/65 nm CMOS devices because of the lack of x, y and z accuracy. In our aim to improve the TLS based fault isolation method, we have studied thermal time-constant signatures using a Modulated Optical Beam Induced Resistance Change (MOBIRCH) technique that may provide accurate x and y submicron resolution as well as depth or z-information of defects in the interconnection part of devices. Both Modeling and measurement results indicate that OBIRCH signal phase shifts and heat-up & cool-down time constants indeed do correlate with the location, dimensions and density of the structures studied.