Production had been halted on an electronic system due to sudden and unexplainable shifts in the resistance values of some Cermet poteniometers. This paper describes the method used to confirm that the problem was due to an ESD environment.

The task of differentiating precisely between EOS and ESD failures continues to be a challenging one for Failure Analysis Engineers. Electrical OverStress (EOS) failures on the die surface (burnt/fused metallization) of an IC can be characterized mainly by the discoloration at the site of the failures. This is in direct contrast to the lack of discoloration characteristic of ESD failures, which occur almost exclusively below the die surface (oxide and junction failures). To aid in this distinction, this paper attempts to present the underlying physics behind the discoloration produced in the EOS failures. For the EOS failures, the metal fuses due to the longer pulse widths (sec to msec), while for the ESD failures, the silicon melts because of the shorter pulse widths (< < 500 nsec) and higher energy. After EOS, the aluminum surface becomes dark and rough and the oxide in the surrounding area becomes deformed and distorted, resulting in the discoloration observed in the light microscope. This EOS discoloration could be due to one or more of the following: 1) morphological and structural changes at the metal/glass interface and the glass itself; 2) changes in the thickness and scattering behavior of the glass and metal in the failed areas.

During the ESD testing of a Dual T1/E1 line interface unit (LIU) at Level One, the circuitry in every pad cell was found to be robust to Electro-Static Discharge (ESD) threshold of up to 2000 Volts. Device failure was however observed on devices when functional tests were performed. These failures were observed on devices which were only subjected for 1250 Volts of ESD stress. The failure analysis revealed ESD induced damage at the Gate - Drain region of a MOSFET in the core of the die. A weak power supply clamp in the supply circuit caused this failure. The step by step analysis process and the redesign of this device with confirmation on new design revision is explained.