The semiconductor industry continues to challenge designer’s ability to provide adequate protection for ESD by scaling to ever-smaller geometries. The metal lines used to connect these circuit elements are also scaled. The effect of non-destructive ESD events on aluminum metal lines is investigated showing a reduction in electromigration lifetime for ESD events close to the failure threshold of the metal. The mechanism contributing to the reduction is a change in the microstructure of the metal resulting in void formation similar to traditional electromigration damage rather than melting and crystallization into smaller grains.

Continuous improvements over time to a CMOS Flash Memory technology resulted in significant improvement in Human Body Model (HBM) ESD immunity for “I/O’s” to Vcc power supply and Vss ground pins. Remaining low level failure modes in the die core included elevated standby current that in some cases could not be localized even with extensive chip de-processing. In addition an apparent functional failure upon post stress ATE test was isolated for certain part revisions. Routine separation of Vss/Vcc supply pin combinations from “all other pins” during HBM ESD test allowed identification of the several failures occurring in the die core. Failure analysis and corrective action is described. Additional diagnostic testing using separate polarity HBM pulses aided in tracing the conduction path causing the apparent functional failure and prompted investigation of HBM tester dynamic properties. It was determined that the magnitude of the “second” HBM pulse in certain testers was sufficient to cause a false powerup condition which results in apparent functional failure upon subsequent ATE test. In-situ monitoring of the Floating Power Bus response (in this case Vss) during application of HBM stress to the Input-pad to Vcc-pin combination revealed a transient caused by the “second” pulse that allowed such apparent failures to be invalidated. Further more, monitoring the in-situ floating Vss bus response to the HBM allowed conclusions to be drawn as to the utility of different power bus and Vss/Vcc supply clamp layouts, thereby allowing improvements to die layout to be implemented.

The IC industry continues to find ways to improve the ability to correlate the electrical failure signature of devices with the physical failure location using different techniques. The purpose of this work is to show that improved transmission line pulse (TLP) testing technique of ESD (ElectroStatic Discharge) protection structures can provide accurate identification of leakage current to better identify where ESD stress testing should stop and failure analysis should begin. Besides the traditional current and voltage measurements at the Device Under Test (DUT), this new TLP testing technique includes the ability to correct for the measurement system losses for improved accuracy. The pulse width of the TLP is chosen to provide the same current amplitude damage level (electrical) as is found in the Human Body Model (HBM) ESD stress testing. This allows a one to one correlation between the two methods and hence the means to correlate the electrical damage of the device and the physical location of the failure site. An SCR (Silicon Controlled Rectifier) device is used as an example.

The intent of this work is to demonstrate the importance of charged device model (CDM) ESD testing and characterization by presenting a case study of a situation in which CDM testing proved invaluable in establishing the reliability of a GaAs radio frequency integrated circuit (RFIC). The problem originated when a sample of passing devices was retested to the final production test. Nine of the 200 sampled devices failed the retest, thus placing the reliability of all of the devices in question. The subsequent failure analysis indicated that the devices failed due to a short on one of two capacitors, bringing into question the reliability of the dielectric. Previous ESD characterization of the part had shown that a certain resistor was likely to fail at thresholds well below the level at which any capacitors were damaged. This paper will discuss the failure analysis techniques which were used and the testing performed to verify the failures were actually due to ESD, and not caused by weak capacitors.