Experimental devices in a deteriorated state were encountered after 168 hours of inductive operating life stress, (IOL) testing. A metal grain boundary breakdown mechanism was found during the analysis of the device, which was creating a low resistance current path between terminals. The AlSiCu top metal was breaking down along the grain boundaries. In addition there was alloying of the Aluminum into the underlying silicon. This alloying was creating a short to the gate, source, and drain. Several variations in the metal stack, testing conditions, number, and dimensions of bond wires die size and mold compound were evaluated to better understand the cause of the inability to withstand IOL stress and to provide a process solution. The prevention of the AlSiCu front metal grain boundary breakdown during inductive life stress testing required a die size, bond wire dimension, and testing condition change to meet the performance specification. This change resulted in a reduced grain boundary breakdown and consequently prevented Al grain boundary breakdown, TiW barrier breakdown, and Al alloy spiking. The die change and modified testing conditions resulted in a successful pass through the IOL stress testing.

One challenge in failure analysis of microelectronic devices is the localization and root cause finding of leakage currents in passives. In this case study we present a successful approach for failure analysis of a diode leakage failure. An analytical flow will be introduced, which contains standard techniques as well as SQUID (superconducting quantum interference device) scanning magnetic microscopy and ToFSIMS as key methods for localization and root cause identification. [1]

Temperature and humidity dependent reliability analysis was performed based on a case study involving an indicator printed-circuit board with surface-mounted multiple-die red, green and blue light-emitting diode chips. Reported intermittent failures were investigated and the root cause was attributed to a non-optimized reflow process that resulted in micro-cracks and delaminations within the molding resin of the chips.

This paper presents the result of a study of a particular failure mechanism of BaTiO3 MLCC (multiple layer ceramic capacitor). A unique technique of cross-section alternating with emission microscope analysis is developed to precisely locate the failure site for capacitors exhibiting low leakage current in μA range. Thermal Imaging Microscope, Photon Emission Microscope, SEM, STEM/EDS and TEM electron diffraction pattern are employed for the characterization of these low leakage failures. Evidence of high concentration impurities are detected in the dielectric layer of BaTiO3 grain boundaries as well as inside certain grains. TEM diffraction imaging at the failure site shows distinguishingly different diffraction patterns within the matrix of BaTiO3 crystal structure. The evidences point to a combination of impurities at grain boundaries and BaTiO3 crystal change induced by impurity as the failure mechanism.

This paper reports on a setup and a method that enables automated analysis of mechanical stress impact on microelectromechanical systems (MEMS). In this setup both electrical and optical inspection are available. Reliability testing is possible on a single chip as well as on the wafer level. Mechanical stress is applied to the tested structure with programmable static forces up to 3.6 N and dynamic loads at frequencies up to 20 Hz. The applications of the presented system include the postmanufacturing test, characterization and stress screens as well as reliability studies. We report preliminary results of long-term reliability testing obtained for a CMOS-based stress sensor.

Freescale Semiconductor is employing a new, multi-layer integrated seal (IS) on its next generation accelerometers. The IS, which encloses the moveable sensing element, consists of alternating layers of poly-Si and PSG. A technique needed to be developed to remove the integrated seal in order to permit failure analysis. Mechanical methods were attempted first, but these resulted in severe damage to the sensing element. Chemical deprocessing was considered, but eventually abandoned because there seemed to be no way to protect the sensing elements from the wet etchants that would be used on the IS. Eventually, Reactive Ion Etching (RIE) with an Inductively Coupled Plasma (ICP) source proved to be a successful means for removing the IS without impacting the sensing element. As the design of the integrated seal underwent multiple redesigns, the removal process was successfully modified multiple times to comply with these changes. By using the right gases in the correct order, a high level of selectivity was maintained, allowing for removal of successive layers of different materials (poly-Si, PSG) without harming the sensing element. After removal of some IS designs, a wispy residue was observed on the sensing element and remaining IS support pillars. Chemical analysis identified this material as a by-product of the RIE process, and methods were devised to eliminate it.

There is a problem with testing torroidal or encapsulated transformers for their DWV characteristics in that the core is normally inaccessible. For high voltage transformers, knowing whether or not the core is sufficiently insulated to prevent breakdown is crucial to the component reliability. If there is a lack of dielectric material between any winding set and the core, it is impossible to determine potential failure susceptibility by the normal DWV testing means. Using MILT- 27’s “Corona discharge” test circuits for this determination requires special equipment, “corona free” capacitors, and has other issues. I have developed a screening method using a Fluorescent Lamp Supply “drive box” with a sinusoidal output from 2 to 7KVpp at or above 25 KHz that will expose corona in transformers when directly back driven into the secondary windings. Transformers that do not have sufficient insulation between winding sets and windings to core can develop corona discharge which can be seen on an oscilloscope via a commercially available isolated current probe as high frequency spikes modulating the original sine wave, heard on an AM radio the same as lightning or static discharge, or cause complete collapse of the voltage at test voltages within seconds when tested up to the rated voltage of the particular winding set. A sample set of 80 transformers was tested, and a 30 percent failure rate was discovered.

Autoclave Stress failures were encountered at the 96 hour read during transistor reliability testing. A unique metal corrosion mechanism was found during the failure analysis, which was creating a contamination path to the drain source junction, resulting in high Idss and Igss leakage. The Al(Si) top metal was oxidizing along the grain boundaries at a faster rate than at the surface. There was subsurface blistering of the Al(Si), along with the grain boundary corrosion. This blistering was creating a contamination path from the package to the Si surface. Several variations in the metal stack were evaluated to better understand the cause of the failures and to provide a process solution. The prevention of intergranular metal corrosion and subsurface blistering during autoclave testing required a materials change from Al(Si) to Al(Si)(Cu). This change resulted in a reduced corrosion rate and consequently prevented Si contamination due to blistering. The process change resulted in a successful pass through the autoclave testing.

Hot electron induced beta degradation has been observed from fiber optic transistors after multiple parametric testing. Beta degradation originated from increasing base leakage current due to the multiple testing. Base leakage current increases were directly related to the hot electron phenomenon at Si-SiO2 interface layer. The hot electron effect broke down the trivalent silicon and its hydrogen compounds (SisH) at the interface layer, which created mobile interstitial hydrogen atoms (Hi) and trivalent silicon atoms Si* (interface trap charges) at the same time. Typically, the SisH forms during the post metallization anneal. This paper will outline the following topics: 1.) The generation of mobile hydrogen atoms and trap charges at the Si-SiO2 interface due to the hot electron phenomenon and its relationship to transistor beta degradation. 2.) A quantitative analysis of hydrogen atoms measured by Secondary Ion Mass Spectrometry (SIMS), and a direct relationship model between beta degradation and hydrogen profiles at the interface layer. 3.) Experimental result showing transistor beta recovery as well as the repopulation of the hydrogen atoms at the interface layer after low temperature annealing (150 °C to 200 °C bake).