Abstract High performance IC's have driven the semiconductor industry towards the sub-nanometer technology nodes for several years. At 16nm and beyond, the spatial resolution and sensitivity of some diagnostic equipment used for failure analysis have reached certain limitations. The accuracy of isolating a faulty signal in a tightly packed group of transistors in a die becomes more challenging. However, with the improvement of SIL (Solid Immersion Lens) based lens technology with higher N.A. (Numeric Aperture), combined with precision die thinning process, allowed some very promising results. This paper demonstrates successful diagnostic techniques utilizing the SIL lens and a variety of die thinning preparation techniques on 7nm and 16nm process nodes in both monolithic and 2.5D SSIT (Stacked Silicon Interconnect Technology) packages.

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

Abstract Temperature dependent failures are some of the most challenging cases that will be encountered by the analyst. Soft Defect Localization (SDL) is a technique used to analyze such temperature-dependent, ‘soft defect’ failures [1]. There are many literatures that discuss this technique and its different applications [2-7]. Dynamic Analysis by Laser Stimulation (DALS) is one of the known SDL implementations [8-11]. However, there are cases where the failure is occurring at a temperature where the laser alone is not sufficient to effectively induce a change of device behavior. In these situations, the analyst needs to think out of the box by understanding how the device will react to external conditions and to make necessary adjustments in DALS settings. This paper will discuss three cases that presents different challenges such as performing DALS analysis where the failing temperature is too high for the laser to induce a change of behavior from ambient temperature, cold temperature failure, complex triggering (Serial Peripheral Interface, SPI), and using an internal signal as input for DALS analysis. The approach used for a successful DALS analysis of each case will be discussed in detail.

Abstract Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

Abstract In this paper, we present application of the SDL technique towards full root cause analysis of functional and structural failures from BIST, SCAN etc. on AMD’s advanced Silicon-on-Insulator (SOI) microprocessors based on a 90 nm process technology node. The devices were exercised at speed using production testers. SDL is used on these microprocessors with failure modes which pass at a lower temperature/voltage but fail at higher temperature/voltage or vice versa to isolate the failing logic/node. The SDL sites are examined for a full root cause analysis and possible process improvements.

Abstract The common Passive Voltage Contrast (VC) localization method has its limits in the case of substrate contact chains. Because of leakage currents it is not possible to charge up the open part of the chain. In two case studies it is shown, how the Active Voltage Contrast (AVC) method in FIB and SEM can help to localize faults in such structures.

Abstract Light emission [1,2] and passive voltage contrast (PVC) [3,4] are common failure analysis tools that can quickly identify and localize gate oxide short sites. In the past, PVC was not used on electrically floating substrates or SOI (silicon-on-insulator) devices due to the conductive path needed to “bleed off” charge. In PVC, the SEM’s primary beam induces different equilibrium potentials on floating versus grounded (0 V) conductors, thus generating different secondary electron emission intensities for fault localization. Recently we obtained PVC signals on bulk silicon floating substrates and SOI devices. In this paper, we present details on identifying and validating gate shorts utilizing this Floating Substrate PVC (FSPVC) method.

Abstract Passive voltage contrast (PVC) is a phenomenon seen while inspecting a semiconductor device where imaged circuit features have a different value of contrast depending on whether that feature has an electrical path to ground, another circuit element, or has an open connection. A common method of fault isolation during failure analysis is to use these contrast values to determine if a feature is incorrectly connected indicating a defect is present. This paper discusses a fault identification method by creating a simulated PVC reference that can be displayed next to the scanning electron microscope PVC image for a comparison of the expected PVC. The procedure of how to create the PVC reference is discussed using functions found in tools typically used to run a Design Rules Check in commonly available software. Three examples are given of how this methodology could be used to provide further analysis capabilities during fault isolation.

Abstract As silicon manufacturing processes move to smaller feature sizes, new silicon fault isolation and debug challenges arise. This paper presents a methodology for silicon fault isolation/debug that allows for simultaneous probing of multiple locations on the die using static infrared emission logic state imaging. Recent tool enhancements leading to more efficient fault isolation and debug are reviewed. Cases are presented from debug of 65nm products showing how this methodology was used to achieve very low throughput times on a variety of complex new failure mechanisms.

Abstract Single column failure [1], one of the complex failure modes in SRAM is possibly induced by multiform defect types at diverse locations. Especially, soft single column failure is of great complexity. As physical failure analysis (PFA) is expensive and time-consuming, thorough electrical failure analysis (EFA) is needed to precisely localize the failing area to greater precision before PFA. The methodology involves testing for failure mode validation, understanding the circuit and using EFA tools such as IR-OBIRCH (InfraRed-Optical Beam Induced Resistance CHange) and MCT (MerCad Telluride, HgCdTe) for analysis. However, the electrical failure signature for soft single column failure is usually marginal, so additional techniques are needed to obtain accurate isolation and electrical characterization instead of blindly looking around. Thus in this discussion, we will also present the use of internal probing techniques like C-AFM [2] (Conductive Atomic Force Microscopy) and a nanoprobing technique [3] for characterizing electrical properties and understanding the root cause.

Abstract Even though failure analysis performed with a latest generation Phemos 2000 Optical Beam Induced Resistance Change (OBIRCH) tool has given excellent results for 120nm and 90nm technology developments, the limitations of tool and technique become apparent when used for the 65nm technology node and beyond. This article discusses the use of a pulsed laser in combination with a lock-in amplifier for OBIRCH-based fault isolation in latest generation CMOS devices. Using such set-up with appropriate settings for laser pulse frequency, scan speed, and phase shift off-set, a ten-fold signal-to-noise ratio gain is achieved. This improved S/N ratio allows detecting faulty circuitry with higher sensitivity and isolating faults that cannot be detected with the traditional OBIRCH set-up. Various case studies on latest technology devices are presented to illustrate the interest of adding the lock-in capability to the standard OBIRCH tool.

Abstract With high implant doses, strained silicon technologies and shrinking feature sizes, dislocation related failures seem to gain more importance in advanced CMOS devices. On the basis of case studies, different types of dislocations as well as the electrical characteristics of the corresponding devices will be presented.

Abstract Bridging faults are a common failure mechanism in integrated circuits and scan-based diagnosis does a good job of isolating these defects. Diagnosis, however, can sometimes result in large search areas. Typically, these areas are caused by long repeater nets. When this happens, physical failure analysis will become difficult or impossible. This paper concerns itself with using a bridging fault analysis as a means of reducing these large search areas.

Abstract Owing to the configuration of cavity up and stacked die packaging and the requirements of backside analysis, both packaging types require similar sample preparation steps. This article describes the failure analysis (FA) process to be applied with cavity up and stack die packages. The FA process flow includes testing to determine the nature of the failure, failure correlation to chip and/or internal circuitry, die preparation for repackaging, die repackaging in a cavity down configuration, automated test equipment (ATE) testing to verify the integrity of the pre-packaging failure mode, backside thinning, global fault isolation, backside reconstruction, and defect identification by front side deprocessing. ATE FA can often be performed using special analysis modes and the modification of the test software to put tester in a halt or a loop during fault isolation. When this is completed, global FA techniques can be used. The article also presents a case study on the successful repackaging efforts of cavity up packages.

Abstract In modern integrated circuits (IC) using sub-micron or deep sub-micron process rules, substrate dislocation is a common failure mechanism in SRAM or embedded SRAM products. Depending on the position of substrate dislocation in the SRAM cell, it may result in problems including junction or contact leakage, gate oxide early breakdown, low threshold voltage, and poor data retention. In this paper, we’ll focus on the test methodology and physical failure analysis to dig out the failure mechanism, substrate dislocation under SRAM pass gate and node contact. In addition, we will measure the electrical behavior of such substrate dislocation. Several FA techniques, such as Passive Voltage Contrast (PVC) [1] pad deposition by Focus Ion Beam (FIB), and electrical micro probing [2] will be used during leakage verification and measurement.

Abstract This paper defines environmentally induced probe drift and elaborates on the problems and challenges associated with it as they relate to physical sub-micron fault isolation systems. Vibration, acoustical, and thermal disturbances are discussed. Probing hardware that can be affected by environmental conditions will be summarized. A comparison of the different approaches is presented with the “pros” and “cons” of each approach summarized. Optimal methods of managing probe drift are presented to give the reader a complete understanding of how environmentally induced probe drift may impact their own physical sub-micron fault isolation. Examples, images, and device data are presented when appropriate.

Abstract The introduction of p+ implanted areas at the drain side of source-drain-gate salicide-blocked electro-static discharge (ESD) protection diodes resulted in a better ESD robustness, however at the expense of increased leakage currents in up to 40% of the 90nm technology test structures. Leaky devices are found to be randomly distributed across a wafer. The leakage current exhibits only weak temperature dependence and is linearly increasing with the p-implanted area. Photoemission microscopy revealed spots located exclusively in the p+ implanted areas. TEM imaging visualized, that the leakage path is caused by dislocations, reaching from the silicon surface through the p+n junction zone into the substrate. Based on these results and the implant conditions, a theory of dislocation formation was postulated and countermeasures had been defined.

Abstract Single bit failures are the dominant failure mode for SRAM 6T bit cell memory devices. The analysis of failing single bits is aided by the fact that the mechanism is localized to the failing 6T bit cell. After electrically analyzing numerous failing bits, it was observed that failing bit cells were consistently producing specific electrical signatures (current-voltage curves). To help identify subtle bit cell failure mechanisms, this paper discusses an MCSpice program which was needed to simulate a 6T SRAM bit cell and the electrical analysis. It presents four case studies that show how MCSpice modeling of defective 6T SRAM bit cells was successfully used to identify subtle defect types (opens or shorts) and locations within the failing cell. The use of an MCSpice simulation and the appropriate physical analysis of defective bit cells resulted in a >90% success rate for finding failure mechanisms on yield and process certification programs.

Abstract Near-infrared laser stimulation techniques such as OBIRCH, TIVA, OBIC and LIVA are now commonly used to localize resistive defects from the front and backside of ICs. However, these laser stimulation techniques cannot be applied to dynamically failed ICs. Recently, two laser stimulation techniques dedicated to dynamic IC diagnostics have been proposed. These two techniques, called Resistive Interconnection Localization (RIL) and Soft Defect Localization (SDL), combine a continuous laser beam with a dynamically emulated IC. The laser stimulation effect on the circuit is monitored through the applied test pattern pass/fail status. This paper presents the methodology to move from static to dynamic laser stimulation. The application of such Dynamic Laser Stimulation (DLS) techniques is illustrated on dynamically failed microcontrollers.

Abstract The failure analyst is often times challenged with the analysis of devices that fail due to speed degradation. These are units that pass the entire standard test program as long as the speed at which the device is tested is kept below a certain level. Many times, these units are binned and sold to customers at reduced prices. The unresolved rate for these types of failures is often sporadic and at times there isn’t any defect that is physically observable or detectable with global EFA (electrical failure analysis) techniques. These devices are usually from an advanced process where a shift in performance such as current, voltage, and speed (frequency) is common.