Soft defect localization (SDL) is a fault isolation (FI) technique used to root cause device marginalities and/or defects. The variety of test modes and their marginalities that can be solved with SDL is increasing as we find new ways to utilize this technique to our needs. However, SDL analysis can be time consuming if the test times are slow since millions of test executions are needed to get a statistically significant result. To solve this problem, we propose an improvement named software automated intelligent laser scanning (SAILS) to modulate laser dwell time on the fly. This software and hardware implementation can be applied to any test method, now or in the future, and to any of the SDL tools available in the market. In this paper, we discuss the successful implementation of this approach and show its ability to judiciously mask out sites in real-time and use this mask to modulate laser dwell time.

Laser probing (LP) has traditionally been used with high-bandwidth oscilloscopes to gather transistor toggling data, providing picosecond-level temporal accuracy. However, this method requires longer acquisition time, making it less favored compared to other fault isolation (FI) techniques. This paper presents an innovative approach to LP using a high-speed digitizer, which significantly reduces the overall LP cycle time. Practical use cases and recommendations for implementing this method are also discussed, highlighting the benefits of using high-speed digitizers in LP for fault isolation.

Non-destructive electrical fault isolation (FI) techniques such as emission- and laser-based techniques have been utilized widely for chip-level failure analysis (FA). However, these techniques by themselves can sometimes be inadequate for certain failure modes. In this paper, we present six FA case studies using Time-Domain Reflectometry (Electro-optical terahertz pulse reflectometry) in combination with the traditional FI techniques.

Photon Emission Microscopy (PEM) is a popular technique for microelectronics failure analysis by detecting the photon emission from a defective circuit, when a failing device is electrically exercised at certain voltage. The photon emission contains physical location information, photon emission spectral information and photon emission intensity information. People often use the physical location information to localize a defective circuit and guide the follow-up physical failure analysis to find the defects. However, this procedure does not always work. Sometimes, it shows no defect found (NDF). In this paper, we propose a new computer vision-based analysis of the photon emission intensity for identifying the root cause of the excessively high IDDQ at elevated Vdds. The procedure includes collecting photon emissions at different Vdds and a follow-up photon emission intensity analysis with computer vision techniques. The procedure was applied on a case of microprocessor chip. After analyzing the dependencies of photon emission intensity on Vdd for 4 types of circuits, it was concluded that the SRAM circuit leakage is the root cause of the excessively high IDDQ at elevated Vdd.

In this paper, we demonstrate three approaches to enhance the topographical contrast of infrared images obtained from lockin thermography (LIT). Infrared imaging, particularly LIT, is one of the extensively used techniques for failure analysis (FA) in the semiconductor industry. However, low-contrast topography images are obtained at room temperature from conventional LIT due to poor emissivity contrast in the devices and the limitation on the performance of the infrared camera. The gray-scale topographical contrast is improved by 85% when the device under test is heated from room temperature to 75°C, using a printed circuit board heater. Furthermore, a heat-assisted LIT approach is proposed and demonstrated at the die level on an electrically leaky silicon interposer sample. The topographical contrast and the signal intensity of the hotspot obtained are enhanced when compared to the classical LIT, which is performed at room temperature. Further, the dual LIT approach is developed to reduce the thermal budget of the heat-assisted approach. The hotspot amplitude and improved topography image are obtained from two consecutive lock-in measurements. In addition, the topography image from this technique is obtained by averaging several hundred frames from the camera for a period of ten minutes, which results in an image that is less susceptible to input noise levels. To increase the throughput of the FA process, quadrature lock-in thermography, a dual-purpose measurement technique is shown. A high-contrast topography image and the hotspot location are obtained from the same lock-in thermogram by performing trigonometric conditioning. The throughput from this approach is the same as the classical LIT technique.

Physical Failure Analysis (PFA) is essential for SRAM yield learning, especially in new technologies or FAB transfers. For this to be successful, physical coordinates for tested bitcell failures must be accurately calculated and verified. The timeline for this process can vary dramatically based on the extent and complexity of any issues. This paper details the successful use of fault localization on isolated, voltage sensitive failures to achieve confidence in verification of physical location prior to PFA.

With the introduction of flip-chip technology, optical-based failure analysis techniques have played a critical role in many failure analysis (FA) laboratories. This is due to the unhindered access for photons to probe or emit from the transistor layer through the bulk silicon. Among the optical techniques, laser voltage imaging (LVI) and laser voltage probing (LVP), collectively called LVx, dominate because they directly expose the electrical activity of a given circuit or cell.

Infrared lock-in thermography systems are frequently utilized for non-destructive failure analysis of integrated circuits due to sensitivity of the thermal detector to small temperature changes from electrical activity. This thermal sensitivity can also be leveraged for design verification and debug of device thermal management via absolute temperature mapping. The application of temperature mapping to a device under test (DUT) that requires boards and sockets, such as in tester based applications, has traditionally been challenging, due to the requirement that the DUT not be moved and the difficulty of heating the DUT through the thermal mass of the boards and sockets to which the DUT is mounted. This paper describes a proposed alternative single-temperature in-situ calibration method to eliminate the need for a heated thermal chuck for absolute temperature mapping. Preliminary results are promising and show that the new alternative single-temperature in-situ method results in temperature measurements within 1 °C close to room temperature and within 2.5 °C at elevated temperatures up to approximately 75 °C, as compared to the 1 °C accuracy of the current standard two-temperature in-situ method. While this alternate method is not as accurate as the standard two-temperature in-situ calibration method, the fact that it can be performed at a single room temperature means that it enables absolute temperature mapping for use cases requiring boards or socketed DUTs, as is the case for tester applications. An example characterization of a DUT utilizing varying clock signal inputs shows the added flexibility and ease of setup that the alternative single-temperature workflow brings, creating new opportunities for use-cases such as boards and testers where the use of a heated thermal chuck is not viable.

Recently, electron beam probing (EBP) has had a resurgence in failure analysis communities due to its clear resolution advantage compared to optical techniques. This paper describes an approach for a detailed advanced logic e-beam probing system, capable of measuring both high bandwidth waveforms and frequency maps. An investigation of optimizing the signal-to-noise of the pulsed beam is presented. By minimizing the working distance and the use of quadrature signal analysis, the e-beam prober is capable of high bandwidth and high-resolution data with adequate signal-to-noise. The use of such system provides a scalable solution for electrical failure analysis for advanced logic integrated circuits.

Thermal Laser Stimulation (TLS) is employed extensively in semiconductor device fault isolation techniques such as TIVA (Thermal Induced Voltage Alteration), OBIRCH (Optical Beam Induced Resistance Change), SDL (Soft Defect localization), CPA (Critical Parameter Analysis), LADA (Laser Assisted Device Alteration), and LVI (Laser Voltage Imaging), etc. To investigate the TLS effects on 7nm FinFET transistor parameters, several transistors of 7nm FinFET inline ET (Electrical Test) macros were tested while employing TLS of various energy values. The test was done in linear mode so that the joule heating caused by the electrical current would be minimized. The experimental results showed that both NFETs and PFETs experienced increased Ioff (Off current) and Sub_Vt_lin_slope (Subthreshold slope), and decreased Ion (On current) and Vt_lin (Threshold voltage) due to elevated temperature of the transistor from TLS. Higher laser power caused greater effects on transistor parameters. The temperature increase on a transistor by TLS depends on the amount of laser energy transferred to, absorbed by, and dispersed by the transistor area. Factors such as the efficient coupling of the SIL (Solid Immersion Lens) with the Silicon backside surface, the transistor size, and the local layout around the transistor will greatly affect the amount of heat delivered to a particular transistor, even while using the same laser power. Thus, setting the laser power for fault isolation with TLS should consider these factors. Our experimental results also showed that the alteration of transistor parameters under TLS was not permanent if the laser power was carefully selected. It should be noticed that during dynamic fault isolation, a transistor may be switching between off, linear mode, and/or saturation mode. The temperature increase on the transistor under TLS may be higher than anticipated due to joule heating if the transistor operation is not confined to the linear region only. Experiments on transistors operating in saturation mode under TLS can be the subject of future work. The results obtained from these experiments can still establish guidelines for laser power settings to be used in the related fault isolation techniques for devices manufactured at the 7nm node so as to achieve non-destructive fault isolation.

Electrooptical investigations such as laser voltage probing (LVP) and dynamic laser stimulation (DLS) are very popular electrical fault isolation techniques (EFI) that use lasers on semiconductor circuits to study the functionality of transistors while the device is in operation. While many studies have been undertaken to understand interaction between laser and planar devices, three-dimensional devices such as FinFETs have interesting physiologies that have not been fully explored. In this work, we study the interaction of polarized light with the n-type metal oxide semiconductor (NMOS) FinFETs, experimentally and through Multiphysics simulations. We report highly directional electrooptical interactions in the FinFET. LVP signals are stronger when the laser used is polarized parallel to the fin and laser stimulation stronger when the laser used is polarized parallel to the gate. These findings affect future laser stimulation and probing investigations for EFI.

Sub-nanometer fabrication processes and advanced packaging solutions such as 2.5D stacked silicon interconnect technology (SSIT) facilitate the production of high-performance ICs, but make physical failure analysis and debugging more difficult. For example, at 16nm, most diagnostic tools reach their limitations in terms of spatial resolution and signal sensitivity and require complex modifications and adjustments. In addition, a higher level of precision and uniformity is required for sample preparation. This paper describes a fault isolation technique that combines solid immersion lens (SIL) technology with precision die thinning. Two failure analysis case studies are presented to demonstrate the method, one a low level negative current leakage failure caused by ESD testing, the other a scan chain failure traced to the input of a delay buffer circuit. In both cases, success is attributed to the resolution and sensitivity of the SIL lens and the ability to precisely control die thickness.

Static random access memory (SRAM) can occupy up to 90% of the die surface in a microprocessor and is often laid out with even more aggressive design rules than logic circuitry, which makes it more prone to manufacturing defects and more sensitive to process variations. As a result, SRAM is often chosen to be the process qualification vehicle during technology development and the yield learning vehicle during product manufacturing. Consequently, fast and accurate analysis of SRAM failure is critical to success on many levels. In this paper, we present a defect identification method that combines design for test (DFT) features, direct bitcell access (DBA), and nondestructive fault isolation techniques. With examples and case studies, it is shown how the approach makes use of electrical failure analysis data to greatly reduce the cycle time of root cause identification in the early stages of new technology development.

Dynamic analysis by laser stimulation (DALS) is a method used to analyze temperature-dependent failures. There are cases, however, where the laser alone cannot get devices hot enough to induce an observable change in behavior. This paper examines three such cases and describes how analysts were able to induce and diagnose the underlying failure by using external signals, complex triggering, and resistive heating to compensate for limitations in laser power.

Depending on the field of application the ICs have to meet requirements that differ strongly from product to product, although they may be manufactured with similar technologies. In this paper a study of a failure mode is presented that occurs on chips which have passed all functional tests. Small differences in current consumption depending on the state of an applied pattern (delta Iddq measurement) are analyzed, although these differences are clearly within the usual specs. The challenge to apply the existing failure analysis techniques to these new fail modes is explained. The complete analysis flow from electrical test and Global Failure Localization to visualization is shown. The failure is localized by means of photon emission microscopy, further analyzed by Atomic Force Probing, and then visualized by SEM and TEM imaging.

In this paper, we present application of the SDL technique towards full root cause analysis of functional and structural failures from BIST, SCAN etc. on AMD’s advanced Silicon-on-Insulator (SOI) microprocessors based on a 90 nm process technology node. The devices were exercised at speed using production testers. SDL is used on these microprocessors with failure modes which pass at a lower temperature/voltage but fail at higher temperature/voltage or vice versa to isolate the failing logic/node. The SDL sites are examined for a full root cause analysis and possible process improvements.

The common Passive Voltage Contrast (VC) localization method has its limits in the case of substrate contact chains. Because of leakage currents it is not possible to charge up the open part of the chain. In two case studies it is shown, how the Active Voltage Contrast (AVC) method in FIB and SEM can help to localize faults in such structures.

Light emission [1,2] and passive voltage contrast (PVC) [3,4] are common failure analysis tools that can quickly identify and localize gate oxide short sites. In the past, PVC was not used on electrically floating substrates or SOI (silicon-on-insulator) devices due to the conductive path needed to “bleed off” charge. In PVC, the SEM’s primary beam induces different equilibrium potentials on floating versus grounded (0 V) conductors, thus generating different secondary electron emission intensities for fault localization. Recently we obtained PVC signals on bulk silicon floating substrates and SOI devices. In this paper, we present details on identifying and validating gate shorts utilizing this Floating Substrate PVC (FSPVC) method.

Passive voltage contrast (PVC) is a phenomenon seen while inspecting a semiconductor device where imaged circuit features have a different value of contrast depending on whether that feature has an electrical path to ground, another circuit element, or has an open connection. A common method of fault isolation during failure analysis is to use these contrast values to determine if a feature is incorrectly connected indicating a defect is present. This paper discusses a fault identification method by creating a simulated PVC reference that can be displayed next to the scanning electron microscope PVC image for a comparison of the expected PVC. The procedure of how to create the PVC reference is discussed using functions found in tools typically used to run a Design Rules Check in commonly available software. Three examples are given of how this methodology could be used to provide further analysis capabilities during fault isolation.

As silicon manufacturing processes move to smaller feature sizes, new silicon fault isolation and debug challenges arise. This paper presents a methodology for silicon fault isolation/debug that allows for simultaneous probing of multiple locations on the die using static infrared emission logic state imaging. Recent tool enhancements leading to more efficient fault isolation and debug are reviewed. Cases are presented from debug of 65nm products showing how this methodology was used to achieve very low throughput times on a variety of complex new failure mechanisms.