The ongoing challenge of test is to obtain high quality at a reasonable cost. Increasing design complexity, signal integrity, and power issues mean that design-for-testability (DFT) and design-for-diagnosibility (DFD) can no longer be treated as an add-on. Similarly, serious attention is needed for parametric testing or the cost requirements for GHz frequency test will be prohibitive. Is the industry ready for the challenge?

This paper describes the use of a Nd:YAG laser to validate logical to physical mapping of embedded arrays found on devices packaged in “flip-chip” configurations.

To deal with failure analysis laboratory tasks, we have developed a modular and smart test system. We demonstrate that Smart Testing Interface can keep a device in the proper electrical state for defect localization. It is a key part of our system and can be easily adapted on a wide range of electrical testers. It offers a unique combination of a slave and a standalone mode. In slave mode, it has a non-disruptive interface between the tester and the component. In stand-alone mode, it is an electrical stimuli generator that can keep the device under test in the correct internal electrical state during IC defect localization. A battery or a power supply powers it up. It can be readily carried in stand-alone mode from one tool to another tool. In stand-alone mode, it has a range of eight hours or more according to the battery capacity and device consumption. We will review a failure analysis laboratory needs and then describe test solutions with our Modular and Smart Test System and a 344 I/O Smart Testing Interface. It is used for EMMI and OBIRCH applications on PHEMOS 1000.

The use of analog blocks in deep submicron intergrated circuits has become commonplace. The process used for these circuits is tuned for pure digital applications. Thus, identification of failures in these blocks requires a detailed understanding of the design, test, and process not previously done with digital failure analysis. This paper will detail the method, results, and solution to a silicided related integral non-linearity in a deep submicron 10-bit DAC.