This paper describes a circuit editing procedure in which the authors used a gallium column Focused Ion Beam (FIB) tool to divide a merged 32nm multi-finger planar transistor into two separate operating components. Rather than rely on live imaging or the various endpoint detection techniques commonly used during an active mill, the authors opted for a ‘blind’ dose-driven technique. The paper explains how the authors made multiple attempts on practice material in order to determine the exact beam placement location and the depth of cut required to perform the operation with a minimum of lateral damage. The loss of a pair of poly gate fingers in the middle of the multi-gate structure seemed to have minimal impact on the final electrical parameters and the separate data paths worked per design specifications.

Backside circuit edit (CE) remains a crucial failure analysis (FA) capability, enabling design modifications on advanced integrated circuits. [1-9] A key requirement of this activity is to approach the active transistor layer of the silicon through the removal of the silicon substrate without exposing or damaging critical transistor features. Several methods have been previously developed to enable or assist with the process with either global or locally targeted techniques for thinning the silicon substrate. These methods employ mechanical methods, laser based techniques (continuous or pulsed), or chemical assisted focused ion beam (FIB) etching to accomplish the thinning. Each of these methods presents different strengths and weaknesses, from their reliability to complexity, but very few techniques provide a precise and accurate quantitative measure of the remaining silicon thickness (RST). Here, we will discuss the use of a FIB with XeF2 for backside Si removal, and the development of an in-situ, accurate measurement of RST.

Widespread adoption and significant developments in Focused Ion Beam technology has made FIB/SEM instrumentation a commonplace sample preparation tool. Fundamental limitations inherent to Ga ion species complicate usage of Ga+ FIB instruments for the modification of semiconductor devices on advanced technology nodes. Said limitations are fueling interest in exploring alternative primary species and ion beam technologies for circuit edit applications. Exploratory tests of etching typical semiconductor materials with Xe ion beams generated from two plasma ion sources confirmed advantages of Xe+ as a potential ion species for gas-assisted etching of semiconductor materials, but also revealed potential complications including, swelling of metal and Xe+ retention within the material arising from excessive Xe ion beam current density.

This paper provides information on ion beam dose delivery and machining a perfect pattern in an ideal world and summarizes the various beam control limitations of the current generation systems. It discusses conventional and proposed solutions to these limitations and highlights their effect on minimum dimension nanomachining applications at the 14 nm Si process node and beyond. The paper highlights the solutions that can be implemented to help negate inconsequential effects of systems. With that in mind, the most significant of these factors in limiting a tool's ability to complete a perfect pattern can be grouped into two categories: timing and placement and non-uniform dose delivery. With good understanding and discipline, most of these issues described can be corrected, significantly minimized, or simply avoided.

Shrinking transistor geometries present ongoing challenges for backside FIB circuit edit operations. The available space to gain access to critical signal lines has diminished to the order of hundreds of nanometers. Several previous works have shown that the diffusion of active devices can be exposed. This paper explores the effects of exposing and selectively damaging the active diffusion layer of advanced finFET process technology. STEM cross section images show that the devices are unaffected when the silicon substrate is on the order of 1-2ums. When the silicon substrate is removed to less than 100nm, the effect can be seen electrically on a set of ring oscillators.

Despite commercial availability of a number of gas-enhanced chemical etches for faster removal of the material, there is still lack of understanding about how to take into account ion implantation and the structural damage by the primary ion beam during focused ion beam gas-assisted etching (FIB GAE). This paper describes the attempt to apply simplified beam reconstruction technique to characterize FIB GAE within single beam width and to evaluate the parameters critical for editing features with the dimensions close to the effective ion beam diameter. The approach is based on reverse-simulation methodology of ion beam current profile reconstruction. Enhancement of silicon dioxide etching with xenon difluoride precursor in xenon FIB with inductively coupled plasma ion source appears to be high and relatively uniform over the cross-section of the xenon beam, making xenon FIB potentially suitable platform for selective removal of materials in circuit edit application.

This paper offers an alternative solution in dealing with Focused Ion Beam (FIB) circuit edit debug of RF products that often required soldering the device onto a test board to enable sensitive RF characterization. Performing FIB circuit edit while the device is soldered on a test board not only eliminates signal degradation and inconsistency caused by a socket; but also, it allows for adding additional FIB edits on the same device. The conventional way of RF product debug of devices in a wire bond package was to characterize the device in a socket, perform the FIB circuit edit, encapsulate the cavity to protect the device from physical & thermal damage, solder the device onto the test board, and then perform post-FIB characterization. This is a very long, one-way process and needs multiple devices for design debug. For RF products in flip chip package, this approach was extremely difficult to almost impossible, because thermal stress of soldering device would significantly deform thinned die. All characterization had to be done with a socket, which often introduced changes of the same magnitude of the parameters of interest as well as repeatability issues. The purpose of this paper is to outline steps to allow for the RF FIB and characterization cycle to be done in a way to decrease throughput time and increase measurement accuracy. True characterization of highly sensitive RF circuit modifications is achieved through: soldering the device to the test board, performing sample preparation, preforming pre-FIB characterization, preforming FIB, and finally preforming post FIB characterization. Elimination of the need to solder a thinned device to a test board allows for the edit location to remain open enabling additional FIB edits to be performed on the same device. This eliminates redundant steps in the device sample preparation and enables quicker throughput times.

Dual-beam focused ion beam (DB-FIB) system is widely used in the semiconductor industry to prepare cross-sections and transmission electron microscopy (TEM) lamellae, modify semiconductor devices and verify layout. One of the factors that limits its success rate is sample charging, which is caused by a lack of conductive path to discharge the accumulated charges. In this paper, an approach using an insitu micromanipulator was investigated to alleviate the charging effects. With this approach, a simple front side semiconductor device modification was carried out and the corresponding stage current was monitored to correlate to the milling process.

Competitive circuit analysis of Integrated Circuits (ICs) is one of the most challenging types of analysis. It involves multiple complex IC die de-processing/de-layering steps while keeping precise planarity from metal layer to metal layer. Each step is followed by Scanning Electron Microscope (SEM) imaging together with mosaicking that subsequently passes through an image recognition and Graphic Database System (GDS) conversion process. This conventional procedure is quite time and resource consuming. The current paper discusses and demonstrates a new inventive methodology of circuit tracing on an IC using known FIB Passive Voltage Contrast (PVC) effects [1]. This technique provides significant savings in time and resources.

To help solve the navigational problem, i.e., being able to successfully locate a circuit for probing or editing without destroying chip functionality, a near-infrared (NIR), near-ultraviolet (NUV), and visible spectrum camera system was developed that attaches to most focused ion beam (FIB) or scanning electron microscope vacuum chambers. This paper reviews the details of the design and implementation of the NIR/NUV camera system, as instantiated upon the FEI FIB 200, with a particular focus on its use for the visualization of buried structures, and also for non-destructive real time area of interest location and end point detection. It specifically considers the use of the micro-optical camera system for its benefit in assisting with frontside and backside circuit edit, as well as other typical FIB milling activities. The quality of the image obtained by the IR camera rivals or exceeds traditional optical based imaging microscopy techniques.

A key capability of focused ion beam (FIB) tools is the ability to deposit conductive materials by introducing organometallic precursors such as tungsten hexacarbonyl [W(CO)6] or (methylcyclopentadienl) trimethyl platinum [C9H17Pt]. The FIB deposited metal is often used in applications such as the modification of integrated circuits (ICs) by creating new electrical connection on the device. The electrical properties of the FIB material are of particular concern to high speed digital and radio frequency (RF) circuit designers because the resistivity of the FIB deposited metal is orders of magnitude higher in value than the near bulk resistivity value of the metals used in IC manufacturing. In this paper, we developed a correlation between the chemical composition of the FIB deposited metal and the electrical resistivity using an effective media theory (EMT) model. Analysis shows that gallium from the ion beam is the dominant contributor to lowering the resistivity of the jumper. The results of this work and model allow us to understand the role the chemical elements play in the electrical resistance of the FIB electrical jumper and to estimate the FIB metal resistance from energy dispersive spectroscopy (EDS) analysis and the geometry.

We present a review of the Low Temperature Ion Source (LoTIS): its aims, design, performance data collected to date, and focused spot size projections when integrated with a FIB. LoTIS provides a Cs+ beam that has been measured to have high brightness (> 10 7 Am -2 sr -1 eV -1 ), and low-energy spread (< 0.5 eV). These source characteristics enable a prediction of subnm focused spot sizes. A FIB with the capabilities enabled by LoTIS would be well-suited to addressing FIB failure analysis tasks such as nanomachining, circuit edit, and site-specific SIMS.

Focused ion beam (FIB) tools for backside circuit edit play a major role in the validation of integrated circuit (IC) design modifications. Process scaling is one of many significant challenges, because it reduces the accessible area to modify transistors and IC interconnects in the design. This paper examines the geometries available for FIB nanomachining, via milling/etching, and deposited metal jumpers by analyzing polygon data from computer aided design (CAD) virtual layers gathered across four process technologies, from 180nm down to 28nm. The results of this analysis demonstrate that the combination of silicon nanomachining box length and FIB via box length identifies the most challenging aspects of the FIB edit. The smallest geometries include a 300 nanometer silicon access area with a FIB milled 200 nanometer via inside it. More advanced technology nodes will require the ability to make smaller geometries without the help of integrated design features typically referred to as design for FIB/Debug.

Gallium focused ion beams (Ga-FIB) have been used historically in the semiconductor industry for failure analysis, as well as circuit edit. However, in spite of the best of these efforts, as integrated circuit dimensions continue to shrink, Ga-FIB induced processes are being driven to their physical limits. The main purpose of this paper is to report the helium and neon ion beams' induced chemistry, including metal deposition, dielectric deposition, and chemically enhanced etching. Two simple examples are shown as proofs of concept demonstrating gas field ion source (GFIS) development for circuit edit applications. The paper summarizes the general utility of helium and neon ion beams for metal deposition, dielectric deposition, and sputtering and etching processes, and discusses some of the technical challenges associated with current GFIS technology. Using GFIS ion beams, it has been observed that the top and buried metal lines can be cut precisely and then reconnected.

The Focused Ion Beam (FIB) technique of internal modification for chip repair, layout verification, and internal signal probe access has become an integral part of the process for bringing advanced products to market. The pervasive switch from wire bond connections to single component flipchip solder bump mounting on high value products has greatly aided the task of FIB editing by placing the bare backside silicon of the die within easy reach. FIB chip circuit access begins with task-specific sample preparation. The package opening and silicon prep process is well defined and quite robust when full thickness chips are mounted to simple ceramic carriers. Unfortunately, the introduction of flexible organic laminate substrates and the development of stacked die packaging has further complicated the process. Multi-chip packages containing combinations of full thickness and thinned chips may be present. They could be wire-bond connected, or use Through-Silicon Vias (TSV) for double sided attachment. Multiple heat treatment cycles joining together materials with vastly different coefficients of thermal expansion (CTE) may result in severe package warpage and stress. All of these conditions and possible combinations have served to invalidate key elements of the established sample preparation process, and made each presented case unique. As the FIB team works to develop new precision techniques for internal circuitry access, the greater semiconductor packaging development and failure analysis community has benefited from the introduction of new tooling and methodologies.

The requirements for focused ion beam (FIB) systems to provide higher image resolution and machining precision continue to increase with the continuation of Moore’s Law. Due to the shrinking geometry and increasing complex structures and materials, it is ever more critical to scale the entire ion probe. The necessity for comprehensive analysis of the ion beam profile and understanding how the ion beam current distribution profile influences different aspects of nanomachining are becoming increasingly important and more challenging.

Focused ion beam (FIB) circuit edit (CE) is an integral part of IC debug, fault-isolation, and low yield analysis. Regarding FIB microsurgery, complexity is growing with the shrinking of dimensions of lower level metallization while the redistribution layer (RDL) structures can increase in all three dimensions. This requires continuous development of CE processes to address these opposite dimension trends and material variations. There are two venues to address CE, accessing from the front side (FS) or from the back side (BS) of an IC. This paper describes the FS techniques and methodologies developed to edit the RDL technology. The goal of this work is to demonstrate on a Cu GND/power plane the performance of the halogen-based contamination process. Results shows that the benefit of reduced time to remove thick Cu metallization is surely advantageous for CE throughput as well as for improving edit success rates.

Metal and dielectric depositions using Xe+ plasma FIB tools are reported and comparisons are made to depositions performed with conventional Ga+ FIB tools. Xe+-deposited Pt had a resistivity of 1250 ± 360 μΩ·cm, similar to the typical range of 1000-2000 μΩ·cm reported for Ga+-deposited Pt. Xe+-deposited dielectric depositions using HMCHS/O2 precursors had an average resistivity of 1.27 x 1019 μΩ·cm (at ± 10V electrical bias), compared to a resistivity of 1.05 x 1014 μΩ·cm for similar Ga+-deposited dielectric films. A comparison between HMCHS/O2 and TMCTS/O2 dielectric depositions was performed for Ga+ systems, and the HMCHS/O2 depositions were found to be orders of magnitude more resistive than the TMCTS/O2 depositions. The experimental difficulties associated with measuring extremely high-resistance films are also briefly discussed.

Sub-nanometer focused inert gas ions derived from a Gas Field Ion Source (GFIS) contain properties that can improve the dimensional and conductivity characteristics of ion beam deposited platinum circuit edit wiring. The following paper, presents ion interaction simulations that help provide insight into the factors which determine the ultimate wire width, resistivity, and metal deposition rates. An experimental result that has aided in the understanding of the primary wire width limiting mechanism is also presented. Finally, a description of the ion beam and precursor properties used for the platinum deposition is provided, a long with a discussion of the wire resistivity measurement technique and challenges. To conclude, the prospects for GFIS ion induced dielectric and metal deposition for circuit edit and nanofabrication applications are discussed.

Pulsed Laser Assisted Chemical Etching (PLACE) is an advanced method of surface preparation that etches backside silicon to ultra-thin remaining layer thickness for Focused Ion Beam (FIB) circuit edit and failure analysis of Wafer Level Packages (WLP). PLACE can achieve ultra-high purity and fine dimensional control since it is a dry process relying on pyrolytic vapor phase reactions initiated, and constrained, by a pulsed laser.