High-power, diode pump laser modules with improved 0.25% antireflective (AR) coating exhibited low (weak) or zero (dead) power emitters after 1000+ hours life-test. Catastrophic optical mirror damage (COMD) was suspected due to a facet coating upgrade but was not physically observed. Electroluminescence ‘fingerprinting’ lent to a contradictory catastrophic bulk damage (COBD) failure mechanism. The Customer wished to clearly understand how an AR coating change caused COBD and not COMD. This paper emphasizes how the astute failure analyst must remain a ‘conscious observer’ deploying concerted analysis steps to truly unmask root-cause amidst conflicted stakeholders.

Non-planar semiconductor devices, such as vertical fin-based field-effect transistor (FinFET) devices have been developed that include multiple vertical fins serving as conducting channel regions to enable larger effective conduction width in a small layout area. However, as circuits are scaled to smaller dimensions, it has become increasingly difficult to improve the performance of FinFET devices. Stacked nanosheet FETs have been developed to further enable larger effective conduction width in a given small layout area while enabling gate length scaling. Nanosheet (NS) FET devices have attracted attention as a candidate to replace FinFET technology at the 5 nm technology node and beyond due to their excellent electrostatics and short channel control. The use of silicon-germanium for the channel material has been explored as a major technology element for FinFET CMOS technology, and the performance benefits of Si-Ge channel over silicon channel have been demonstrated. Compared with conventional FinFET, stacked gate-all-around (GAA) NS CMOS shows higher electron mobility for nFET but lower hole mobility for pFET due to its unique device architecture and carrier transport direction. To improve pFET performance, SiGe NS is proposed as the pFET channel material. However, introducing and maintaining strain in the SiGe GAA NS channel is challenging but important for improving carrier transport. It is critical to understand the strain distribution in the advanced 3D nanosheet FET structures. This paper describes the use of advanced transmission electron microscopy (TEM) techniques to investigate the strain distribution in strained SiGe channel NS pFET through Si channel trimming and selective Si1-xGex epitaxial growth. A stacked GAA NS pFET was fabricated from compressively strained Si1-xGex channel with good crystallinity and high uniaxial compressive stress of ~1 GPa. From lattice deformation maps with a nanometer spatial resolution obtained by TEM techniques, the authors demonstrate that nano-beam precession electron diffraction techniques can be used to investigate the local strain distribution of the stacked GAA NS pFET devices with high precision, and thus help to optimize the integration process and strain engineering for pFET device performance enhancement for the next generation of CMOS logic in GAA NS technology.

In the failure analysis (FA) of an organic light emitting diode (OLED) display device, fault isolation and physical failure analysis (PFA) were used to identify the root cause of display failure. It is challenging to conduct the FA of a display device, as it consists of display panel, a circuit board and components like semiconductor chips and this integration makes the failure complicated and difficult to analyze and understand. In the case of the display failure studied in this paper, the first work of fault isolation did not clearly identify the origin of the malfunction and its PFA didn’t show any specific defects. To precisely identify the defect location before destructive analysis, the fault isolation technique of OBIRCH was applied to the display device and subsequent PFA successfully identified a crack defect causing the display failure. This finding was given as feedback to the wafer fab and processing parameters were adjusted to prevent generation of the defect in the OLED display device.

Power devices are now ubiquitous and integral in control of systems across various sectors of the economy. Silicon-based power devices still dominate in most of the applications although new materials and device architectures are becoming common in the next generation of devices. While several techniques to characterize the overall device properties are necessary, the fundamentals in several of these power devices such as Insulated Gate Bipolar Transistors (IGBTs) still rely on healthy junctions for optimal device performance. The technique of Electron Beam Induced Current (EBIC) is used to examine the depletion zones of the p/n junctions between drift and body regions of the device. Simple sample preparation methods such as cleaving the device allows quick cross-section evaluation of the device structure and electrical characterization using EBIC yields good data. The role of acceleration potential on depletion zone thickness is considered during the analysis of intact die and cross-sections. While low voltage EBIC provides images of the p/n junctions in cross-sections, it is found that high voltage (30 kV) EBIC images can also be used to image these same p/n junctions and therefore may point to a very quick line monitor or means for early failure analysis of these devices.

The instrumentation amplifier products are high-volume runner products hence, also a high volume of returns are encountered at Failure Analysis Department. To solve each return would need a highly structured technique that requires extensive plot of results for the determination of proper failure mechanism. A perceptive approach that the Failure Analyst deal with in solving the different issues encountered is the compilation of failure data using commonality study of returns with summary that can easily be seen on a Measles chart. A compilation of complete list of historical analysis with circuit block layout designation, test methods, signature cases, microprobing and circuit analysis collaboration results are consolidated in one file to help guide the Analyst in determining the exact cause of failure, thus improving quality and turnaround time that translates to cycle time improvement of 56% CT days reduction hence creating value to the customer.

This paper reports the novel application of Plasma Focused Ion Beam (pFIB) to reveal subtle defects in advanced technology nodes. Two case studies presented, both of which alter the standard work procedure in order to find the defects. The first case highlights the precise milling capability of pFIB in discovering the metal buried via void that is easy-to-miss by standard failure analysis (FA) practice. The second utilizes pFIB circuit edit process to facilitate electrical isolation in pinpointing the exact failure location and thus enables identifying the defect more efficiently.

In this work we have investigated the results obtained using fault isolation techniques such as EMMI, OBIRCH and OBIC on a Wide band gap power device and in particular a 4H-SiC. We used YLF laser and Green Laser and showed the differences in the resulting hot spots. In the selected point, FIB cross sectioning and EDS analysis was performed. Once that the defect was shown, the differences the fault isolation results were discussed.

Failure Analysts are often required to work on a vast array of part types. These integrated circuits (IC) can have wide ranging functions and applications. Also, the ICs can be offered in a multitude of package types. All these factors compound the challenges faced by the Failure Analysts. This paper provides a brief snapshot of one approach adopted by the ON Semiconductor Product Analysis Labs to prepare in advance for the products that offer significant challenges in terms of electrical bench testing and fault localization. The approach demonstrates how the prospects of success of a given failure analysis (FA) case can be improved by making available smart solutions that cut down on the effort required for bench testing, defect localization and failure verification activities. This in turn can contribute to cycle time reduction and improve overall efficiency of the FA process.

Computer Aided Design (CAD) alignment is a key requirement for dynamic fault isolation. CAD alignment between the drawn layout and the physical reflected image from the device helps to navigate and observe the physical location of the suspected circuitry. Conventionally, large structures such as the boundaries of Static Random-Access Memory (SRAM) cells are used as reference for coarse CAD alignment and the shallow trench isolation (STI) layer is used for fine alignment while analyzing logic cell structures. With technology scaling, especially into FinFETs, the fine alignment has become more challenging as the reflected optical image of STI layer is poorly resolved. In this paper, we discuss the enhanced CAD alignment techniques in Synopsys Avalon that uses features “Minimum object size (dimension based)”, and “net search” developed in the CAD tool, Synopsys Avalon, combined with Amplitude lock-in Dynamic Photon Emission Microscopy (D-PEM) technique to assist a finer CAD alignment.

Hard functional and logic failures which are insensitive to temperature, voltage, or frequency have become increasingly difficult to debug in advanced technology nodes, especially when Photon Emission (PEM) analysis could not provide any leads and Dynamic Laser Stimulation (DLS) could not be used due to the nature of the failure (no pass/fail margin). Laser Voltage Imaging (LVI), which is an extension of the Laser Voltage Probing (LVP) technique, provides a visual map of active components that are toggling at a certain frequency. This technique is widely employed in scan chain debug due to its simplicity, efficiency, and accuracy. However, most of LVI applications in literature reviews only involve scan chain fault isolation. This paper will present alternative applications for LVI, apart from scan chain debug. One specific application is the debug of a broken signal path by sending a periodic signal as a stimulus to a GPIO pad and tracing the LVI signal through the path by frequency mapping. In this paper, the concept and methodology behind this fault isolation approach will be discussed in full detail. Furthermore, three case studies of different types of hard failures with different applications of LVI will also be presented: an IO functional failure, an ATPG (Automatic test pattern generation) SAF (Stuck At Fault) failure and a BSDL(Boundary scan description language) input interconnect failure, to illustrate how LVI could be deployed in fault isolation for those functional and logic hard failures.