As dynamic random access memory (DRAM) chips grow in density and complexity, tightly packed word lines become increasingly susceptible to interference, potentially causing data retention failures. This study investigates a novel failure mechanism where disconnected buried channel array transistors (BCATs) create interference affecting three adjacent word lines (3row failure). Through systematic analysis of voltage, temperature, and operational sequences, we demonstrate that the pass gate effect significantly impairs dynamic data retention, leading to these 3row failures. Our findings reveal a previously unidentified defect mechanism in advanced DRAM technology and emphasize the importance of comprehensive testing protocols for detecting and characterizing emerging failure modes. This work contributes to the broader effort of improving DRAM reliability in modern computing systems.

A 0.18 µm technology process was observed to generate some damage on polysilicon lines (missing polysilicon lines). This induces mainly an increase in digital scan failure rate. This was attributed to a particular fabrication cleaning tool. Improvement of the process was made. For all the material affected by the missing polysilicon line issue and to secure production, some additional production tests and burn-in were introduced. Few devices were failing digital scan test post burn-in and a very particular failure mechanism was observed. Physical failure analysis was performed on these devices, and it was related again to missing polysilicon located into the reset path of some Flip-Flops. Several improvements of the production test program were done to try to detect these devices pre-burn-in. After a final review it was concluded that the reset path failure could only be detected after burn-in.

This paper describes how lock-in amplifiers and boxcar averaging can overcome limitations in conventional fault isolation techniques for microelectronic testing. Our approach achieves superior results compared to traditional spectrum analyzer methods through three key applications. First, we measure the signal-to-noise ratio of individual pulses during laser voltage tracing (LVT) across varying pulse widths. Second, we leverage enhanced LVT imaging to improve computer-aided design to stage alignment and laser voltage probe placement—a crucial advancement for analyzing compressed scan and streaming scan network test failures. Finally, we present a case where our Lock-In amplifier system successfully generates pass/fail signals for dynamic laser stimulation in scenarios where conventional test hardware proved inadequate.

A series of power supply line controller failures at Analog Devices Incorporated (ADI) exhibited abnormal output voltage and quiescent current symptoms. Our failure analysis revealed a gate-to-drain/source tungsten spur defect, which required a sophisticated multi-step detection process. The investigation combined several advanced techniques: light emission microscopy (LEM) and optical beam induced resistance change (OBIRCH) identified the failing circuit, passive voltage contrast (PVC) located the affected transistor, and nanoprobing with electron beam induced resistance change (EBIRCh) pinpointed the gate-to-source/drain leakage location. Focused ion beam (FIB) cross-sectioning proved crucial for physical analysis, as conventional chemical deprocessing would have destroyed the tungsten spur and potentially misidentified the defect as electro-static discharge damage. Transmission electron microscopy confirmed the spur's composition as tungsten, and subsequent fabrication investigation traced the root cause to a titanium nitride barrier breach at the contact bottom, occurring where contacts intersect with spacer nitride. The issue was resolved through critical dimension tightening at the fabrication site.

There are several variants of artificial intelligence (AI) hardware structures that are under study by the semiconductor industry for potential use in complementary metal–oxide–semiconductor (CMOS) designs. This paper discusses some of the failure analysis challenges that have appeared in discrete test structures and test arrays developed as part of an exploratory phase-change memory (PCM) program at IBM's Albany AI Hardware Research Center.

This paper presents the results of an investigation to gain a better understanding of the impact of wafer substrate copper (Cu) contamination on FinFET devices. A chip from a wafer free of Cu contamination and several chips near a Cu contaminated wafer edge were sampled for chemical, structural, and morphological analysis and electrical device performance testing. The contaminated wafer was also annealed at high temperature, trying to drive Cu diffusion further into the Si substrate. TEM analysis revealed that the Cu interacted with Si to form a stable η-Cu 3 Si intermetallic compound. SIMS analysis from the backside of the wafer detected no Cu even after most of the backside material was removed. Likewise, electrical nanoprobing showed no parametric drift in the FinFETs near the edge of the wafer, comparable to device behavior in a Cu-free Si substrate. These results indicate that the formation of η-Cu 3 Si with a well-defined crystalline structure and stable stoichiometry immobilizes Cu diffusion in the Si substrate. In other words, the impact of Cu diffusion in silicon has no effect on device performance as long as η-Cu 3 Si does not form in the FinFET channel or short any structures within the chip.

This paper provides an overview of the semiconductor analysis process at BMW. It explains how it was developed and how it differs from the failure analysis process used in semiconductor fabs. It describes the general process flow from first analyses through descending levels of localization at different length scales. It discusses sample preparation procedures, test methods and equipment, and advanced techniques. In the work presented here, the authors explain how they combined ToF-SIMS with STEM lamella preparation in a FIB-SEM, which allowed them to correlate concentration variances in an underlying layer with surface anomalies discovered during light microscope inspection.

This paper describes a project to develop and deploy a systematic screening methodology involving computed tomography (CT) to inspect a set of electromagnetic interference (EMI) filter components for a spacecraft application. The goal was to deploy the nondestructive CT test to replace the destructive test method typically deployed for such components. The paper describes the development of test criteria, fixturing, inspection process, and data analysis, including quantitative image analysis of voids and cracks. The initial results indicated that the parts would not pass the requirements established in the test design. A waiver was written to the project clarifying that if the parts were to be used in the assembly, they should be considered as simple conductors with EMI filtering capability viewed as an added benefit rather than a guaranteed design requirement.