Fault localization using both dynamic laser stimulation and emission microscopy was used to localize the failing transistors within the failing scan chain latch on multiple samples. Nanoprobing was then performed and the source to drain leakage in N-type FinFETs was identified. After extensive detailed characterization, it was concluded that the N-type dopant signal was likely due to projections from the source/drain regions included in the TEM lamella. Datamining identified the scan chain fail to be occurring uniquely for a specific family of tools used during source/drain implant diffusion activation. This paper discusses the processes involved in yield delta datamining of FinFET and its advantages over failure characterization, fault localization, nanoprobing, and physical failure analysis.

In this work, two analysis methods for word line (WL) defect localization in NAND flash memory array are presented. One is to use the Emission Microscope (EMMI) and Optical Beam Induced Resistance Change (OBIRCH) to analyze the device through backside, which has no risk of damage during sample preparation. Depending on the I-V characteristics of defects, different analysis tools can be applied. The second method is to analyze a device defect location that is hard to detect through backside analysis. The precise defect site can be localized by Electron Beam Induce Resistance Change (EBIRCH) [1,2], and the defect profile can be observed. The large memory array in NAND flash structure leads to the wide sample movement during EBIRCH analysis. The sub-stage movement function used successfully solves this problem.

The SuperCam instrument was selected by NASA in July 2014 and has been implemented on the Mars 2020 Perseverance rover. This instrumental suite gathers four different remote-sensing techniques including a very compact Infrared Spectrometer (IRS). For several reasons of costs and planning and after a risk mitigation phase, the use of full commercial-off-the-shelf photodiodes from TELEDYNE JUDSON J19 Series as detector for the IRS was decided. This paper describes the procurement, evaluation, and qualification philosophy of these photodiodes, providing information on the subsystems of the SuperCam instrument and the description of these photodiodes. Critical and fragile parts of the photodiode as the thermo electric cooler, have been particularly studied. In conclusion, the component was space qualified using the original use of the particle impact noise detection test applied for a mechanical screening purpose, with correlation between performance and fine leak, screening and the lot acceptance test processes.

The continuously growing demands in high-density memories drive the rapid development of advanced memory technologies. In this work, we investigate the HfOx-based resistive switching memory (ReRAM) stack structure at nanoscale by high resolution TEM (HRTEM) and energy dispersive X-ray spectroscopy (EDX) before and after the forming process. Two identical ReRAM devices under different electrical test conditions are investigated. For the ReRAM device tested under a regular voltage bias, material redistribution and better bottom electrode contact are observed. In contrast, for the ReRAM device tested under an opposite voltage bias, different microstructure change occurs. Finite element simulations are performed to study the temperature distributions of the ReRAM cell with filaments formed at various locations relative to the bottom electrode. The applied electric field as well as the thermal heat are the driving forces for the microstructure and chemical modifications of the bottom electrode in ReRAM deceives.

The paper demonstrates accurate fault isolation information of metal-insulator-metal (MiM) capacitor failures by lock-in thermograph (LIT). In this study, a phase image spot location at a lock-in frequency larger than 5 Hz gives more accurate defect localization than an LIT amplitude image or OBIRCH to determine the next FA steps.

Failure analysis plays a very important role in semiconductor industry. Photon Emission Microscopy (PEM) has been extensively used in localization of fails in microelectronic devices. However, PEM emission site is not necessarily at the location of the defect. Thus, it has limitation for the success rate of the follow-up physical failure analysis focusing on the emission site. As semiconductor technology advanced in the 3D FinFET realm and feature size further shrank down, the invisible defects during SEM inspection are tremendously increased. It leads to the success rate further decreasing. To maintain good success rate of failure analysis for advanced 3D FinFET technology, electrical probing is necessary to be incorporated into the failure analysis flow. In this paper, first, the statistic results of PEM emission sites versus real defect locations from 102 modules of microprocessors manufactured by 14nm 3D FinFET technology was present. Then, we will present how to wisely design electrical probing plan after PEM analysis. The electrical probing plans are tailored to different scan chain and ATPG failures of microprocessors for improving failure analysis success rate without increasing too much turn-around time. Finally, two case studies have been described to demonstrate how the electrical probing results guide the follow-up physical failure analysis to find the defect.

In the failure analysis (FA) of modern semiconductor logic device manufactured in foundry fab, efficient identification of wafer edge’s defect was studied by using volume diagnosis analysis and plasma-focused ion beam (FIB) planar deprocessing. As the chip from wafer edge has multiple defective locations, there is the limitation of the conventional FA work to identify them. Here, we used volume diagnosis analysis to identify the multiple defective locations within chip and plasma-FIB planar deprocessing to delayer those locations and find out defects. The actual FA work verified that new workflow successfully identified the different defects from different layers from the chip of wafer edge and efficiently accelerated the quantity of FA results, importantly leading to more representative status of inline defect.

Passive voltage contrast (PVC) is widely used to detect underlying connectivity issues between metals based on the brightness of upper metals using scanning electron microscopy (SEM) or focused ion beam (FIB). [1] However, it cannot be applied in all cases due to the uniqueness of each case where brightness alone is insufficient to tell leakage location. In this study, propose a simple technique using platinum (Pt) marking as a circuit edit (CE) technique to alter metal PVC to identify the actual leakage location. Conventional SEM and PVC contrast imaging are unable to pinpoint exact defects without data confirming the leakage from nano-probing such as Atomic Force Probing (AFP) or SEM base nano-probing (NP) [2]. Using this method, we can improve the analysis cycle time by direct analysts the defective location in SEM, while also saving tool cost.

This paper presents a backside chip-level physical analysis methodology using backside de-processing techniques in combination with optimized Scanning Electron Microscopic (SEM) imaging technique and Focused Ion Beam (FIB) cross sectioning to locate and analyze defects and faults in failing IC devices. The case studies illustrate the applications of the method for 28nm flip chip bulk Si CMOS devices and demonstrate how it is used in providing insight into the fab process and design for process and yield improvements. The methods are expected to play an even more important role during 20-nm process development and yield-ramping.

The back-end-of-line (BEOL) structure of current IC devices fabricated for advanced technologies is composed of film stacks with multiple interfaces. The requirement of high interfacial strength is therefore necessary between the different layers in the BEOL stacks to ensure device reliability. To enhance the IC performance for new technologies, inter-level dielectric (ILD) made of SiO2 is replaced by low-k and ultra low-k (ULK) dielectrics, which possess a low dielectric constant but have poor mechanical strength. Therefore, the challenge in maintaining BEOL film stack integrity and reliability becomes even greater for advanced technologies. In this paper, we show failure analysis results on a case study of ULK adhesion failure during the IC manufacturing process. The symptoms of the BEOL failure are due to debris dropping on the wafer during chemical mechanical polishing (CMP) after Cu thin film deposition and failure of focusing at wafer extreme edge during the subsequent photolithography process. Extensive mechanical and chemical analyses were conducted on the ULK and adjacent thin films. It was revealed that the interface of ULK and Silicon Nitride from a suspected problematic machine showed abnormally low adhesion energy and high carbon composition. Troubleshooting on that suspected machine found a clog in the foreline. Based on the failure analysis and machine troubleshooting results, the failure mechanism of the case was discussed.

This paper described a gate oxide failure case which affected the electrical parameters such as Vt and Idsat of both HV N&P MOS. A systematic problem solving approach combined with several FA techniques was applied to find the root-cause to be arsenic outgas cross-contamination.

Integrated power devices (IPD, IC+MOSFETs) have gained popularity for their excellent power management performance and compact size. During the development, it was soon found that exposing the multi-die device for debug could be challenging. In the article, we will show how the traditional decapsulation method fails to expose the device properly for follow up analysis. We will then present a new technique using laser ablation + chemical/plasma etch that proves to work for IPD products. We will then present a complete FA example combining this decapsulation technique and many other advanced FA techniques to solve an elusive failure during the development phase of an IPD product.

A PCB trace was repeatedly cracking in the same location. Visual inspection showed cracking there and at structurally similar locations, with solder mask missing from one side of the trace of interest. Fracture analysis suggested that these issues and etch pitting caused crack initiation, followed by fatigue failure that ultimately led to full fracture. A FIB section of a second failure reinforced the finding that the fundamental cracking mechanism was fatigue.

In this paper, a zero yield case relating to a systematic defect in N+ poly/N-well varactor (voltage controlled capacitor) on the RF analog circuitry will be studied. The systematic problem solving process based on the application of a variety of FA techniques such as TIVA, AFP current Imaging and nano-probing, manual layout path tracing, FIB circuit edit, selective etching together with Fab investigation is used to understand the root cause as well as failure mechanism proposed. This process is particularly critical for a foundry company with restricted access to data on test condition setup to duplicate the exact failure as well as no layout tracing available at time of analysis. The systematic defect was due to gate oxide breakdown as a result of implanter charging. It serves as a good reference to other wafer Fabs encountering such an issue.

In this study, a 65nm product level low yield case has been investigated and its failure mechanism was identified. Root cause analysis was discussed and concluded. The product has been hit with ATPG failure with a unique wafer map signature - a butterfly pattern. Tools commonality and timeframe analysis show that the highly suspected process is the Metal1 Cu seed PVD step. To understand the failure mechanism and its root cause, product level FA was needed. However due to its functional failure property, the conventional EFA is not applicable in this case. Instead GDS study was performed to isolate the failure sites. Subsequently physical FA analysis was carried out at the identified sites to reveal its failure mechanism. Metal1 void was observed on the sidewall of the metal1. Meanwhile, a very interesting phenomenon was observed. If die was selected on the left part of the butterfly pattern, the void would be on the right side sidewall of the metal. If the die was selected on the right part, the void would be on the left side sidewall of the metal1. All of the voids were towards wafer center. After in-depth study of the PVD process, we suspect the pass die could also have void. These voids must be also towards wafer center. Subsequent PFA on good unit confirmed our suspect. The more detailed mechanism of the void formation was discussed and evidences supporting our analysis are to be presented in the paper. Nevertheless, the butterfly pattern is still a question in our mind. After in-depth analysis, we found the voids formation was associated with Metal1 orientation. Because of the horizontal orientation of Metal1, if the void happens it should locate in the end of the metal line in the butterfly area. While the majority of Via1/contact are stand on the line end, so the open Via1/contact failure will happen. For the die out of the butterfly area, the majority of the void locates in the sidewall of the metal line center. The majority Via1/contact are not stand in the center of the metal line center, of no Via1/contact open happen. But it is still has reliability concern. Much more detailed and in-depth mechanism is investigated in the paper. Moreover, improvement is also touched on. Systematic problem solving method is employed in this case. It is good reference for same kinds of failure analysis.

With the scaling down of semiconductor devices to nanometer range, fault isolation and physical failure analysis (PFA) have become more challenging. In this paper, different types of fault isolation techniques to identify gross short failures in nanoscale devices are discussed. The proposed cut/deprocess and microprobe/bench technique is an economical and simple way of identifying low resistance gross short failures.

IP protection is of major importance for a semiconductor company and only limited information is made available for device debugging for the product outsourced to a foundry. In order to position ourselves better in the ever competitive semiconductor industry, with the consideration of IP protection, we have to provide the customers with the Si debugging capability and device/chip verification services in foundry. This paper explores the Si debugging methodology and technique in a foundry. Two case studies are presented and discussed. The first case illustrates the isolation of the failure location by InGaAs microscopy, upon which the failure was identified to be caused by a latch-up issue. In the second case, due to confidentiality considerations from the customer, full information could not be provided to the foundry for silicon debugging. The paper illustrates the ability to effectively debug a failure despite being constrained by limited information from the customer.

As semiconductor geometries decrease, the size of a defect that leads to circuit failure also decreases. While many defects will cause photoemission or observable leakage paths, occasionally a defect will occur in an area that cannot be easily analyzed. In this analysis, a yield issue in nickel-silicide (NiSi) piping is investigated. The failure had characteristics that fell into areas that avoided detection. A planar transmission electron microscope of the substrate at the defect site was performed to look for evidence of crystalline defects that would allow a conduction path across the channel. This analysis found that NiSi encroachment was the root cause of the yield issue. All analyzed units had the defect between stacked nFET transistors. Because the defect was between stacked nFET gates, the results show that the failure characterization required control of multiple gates to measure the transistor off-state drain to source current.