We investigated and demonstrated the advantages and limitations of several optical methodologies as valuable silicon failure analysis techniques, and how they could be used in a complementary manner to assist in shortening the diagnostic time.

The migration to smaller geometries has translated to an increase in the number of transistors possible in each integrated circuit. Failure analysis of such complex circuits presents a major challenge to the semiconductor industry and is a driving force behind the considerable interest in nondestructive, cost-efficient, “shortcut” fault isolation techniques. In this paper, we present the application of thermal-induced voltage alteration (TIVA) for failure analysis of 0.11µm technology memory devices and demonstrate the key aspects of this technique. The back side TIVA results are compared with analysis performed using back side emission microscopy (EMMI), and the limitations of EMMI are highlighted. The advantages and limitations of the TIVA technique are also discussed.

OBIRCH analysis is a useful technique for defect localization not only for parametric failures, but also for functional analysis. However, OBIRCH results do not always identify the exact defect location. OBIRCH analysis results must be used in conjunction with other analysis tools and techniques to successfully identify defect locations.

The Soft Bit failure (Single Bit Failure sensitive to voltage) of a 90nm SRAM cell presented a difficult challenge for the Failure Analysis (FA) group. Physical analysis of these Soft SRAM failures did not show any visual defects; therefore the FA required an accurate electrical characterization. The transistor characteristics of the failing SRAM transistors are needed in order to speculate on the possible failure mechanism. The Nano-Probing technique performed at Nice Device Failure Analysis of Laboratory (NDAL) allowed us to identify anomalies of I/V characteristics like Vt imbalance, low Gain, asymmetrical Vt, ID (Drive current) and Ron. Case studies of an asymmetry phenomenon reported here lead to a correlation between the failure mode and the electrical measurements. This paper demonstrates a suitable electrical methodology and characterization by Nano-Probing in order to successfully manage a FA approach on this type of failure.

This paper describes the use of image processing techniques in metrology and failure analysis with the help of three case studies. The first study concerns a technique that significantly automates the process and hence enables both a rapid and accurate extraction of cumulative distribution function for transistor CD through the use of edge detection and quantification of image intensities. The second study is about utilizing a cross correlation algorithm and an appropriately chosen sample and image to estimate the "on image" spatial resolution of an scanning electron microscope. The last case study uses image data acquired with an atomic force microscope. The paper describes how information theoretic concepts like entropy and mutual information combined with image segmentation and nearest neighbor extraction can be used to isolate those regions of the AFM scan that can potentially benefit from further analysis.

In general failure analysis cases, a less invasive fault isolation approach can be utilized to resolve a visual root cause defect. In the case of nano technology, visual defects are not readily resolved, due to an increase in nonvisible defects. The nonvisible defects result in a lower success rate since conventional FA methods/tools are not efficient in identifying the failure root cause. For the advanced nanometer process, this phenomenon is becoming more common; therefore the utilization of advanced techniques are required to get more evidence to resolve the failure mechanism. The use of nanoprobe technology enables advanced device characterization in order to obtain more clues to the possible failure mechanism before utilizing the traditional physical failure analysis techniques.

A standby current failure of the 80nm design-ruled Dynamic Random Access Memory (DRAM) during burn-in stress was investigated. In our case, hot electron induced punch-through (HEIP) of a PMOS transistor was a leakage current source. The bake test is a useful method to identify the mechanism of a standby current failure due to hot carrier degradation.

This article outlines an optimal approach for board level CSP failure analysis, where the chip and printed circuit board are analyzed as a single unit to determine the root cause of the board level failures. A technique using a combination of cross-section and parallel polishing is described in detail. This technique was developed to inspect key aspects of solder joint fatigue, which are solder joint height, pad dimensions, heating profiles or reflow, substrate warpage, and solder joint voids. This technique allows investigation of the above factors in a single sample preparation and readily arrive at the root cause solution in the minimum time. Results showed that package properties, the design of solder pads play the major role in determining how the fatigue behavior of solder joints will affect CSP component. Additional factors like nickel/gold and nickel palladium finishes were found to be more brittle and promote solder joint cracking.

In this paper, an IC failure case by EOS is presented. The optical microscopy, SAM, and X-ray were used for the non-destructive analysis. The decapsulation, SEM, FIB were used for the destructive analysis. It was found that IC’s presented in this case were electrically overstressed (EOS), which caused the uncontrollable overheating. The EOS symptoms can be various, such as electromigration, intermetallic compound formation, delamination on die surface, circuit track damages, and wire bonding broken. The latch-up testing and deprocess technique were used to simulate the failures and it was found that the failures in this case was due to latch-up. The results show that failure symptoms of EOS are various and their identifications require different failure analysis techniques and tools.

Electrical overstress (EOS) is a common failure cause for many of the electronic circuits today. The Failure Analyst has no difficulty identifying EOS as the cause of the failure. The difficulty comes from determining the source of the EOS event so it can be eliminated. This paper describes two case studies looking a gross EOS damage and very mild EOS damage. Close cooperation between the customer and vendor was required to determine the source of the EOS events.

In this paper, we introduce an example of successful failure analysis using combination of several fault localization techniques on a 0.18 um CMOS device. These techniques contain both front and backside localization techniques. Front side techniques are the following: emission microscopy, liquid crystal analysis, and electron beam (e-beam) probing with focused ion beam (FIB) milling. The backside techniques are optical beam induced current (OBIC) and optical beam induced resistance change (OBIRCH). We discuss the fault mechanism, including the relation between the “hot” spot of these analyses and the failure location in the circuit.

This paper introduces a technique to reveal a small feature defect of an SRAM cell via utilizing a 200kV dedicated field emission STEM on a FIB prepared sample. The initial TEM sample contains the entire defective cell; one side of the sample has n-type transistors and the other p-type. Both sides of the sample were observed using STEM bright field and dark field (HAADF) detectors (transmitted beam – inner information) and SEM mode (surface and sub-surface information). With deep beam penetration of STEM, one contact was found to be very close to the poly gate. Further FIB cuts were performed to remove the rest of the bulk away from the defect, thinning down to the area of interest. When the sample was thinned to a final thickness of less than ~100nm, a final image was taken of the exposed defect. The failing root cause was that the upper corner of the poly had touched the adjacent contact. Such an approach offers many unique advantages for site specific failure analysis over conventional SEM and/or TEM techniques.

As integrated circuits’ geometry are reduced by about 0.7 for each new generation, failure analysis becomes more challenging in fault isolation and physical deprocessing to determine the root cause of the failure. It is impossible to deprocess the device by conventional wet-etch method as metallization tends to be etched or lifted off using all known wet chemicals. Currently the deprocessing techniques can be classified into two categories: dry-etch plus mechanical polishing and full dry-etched methods. In Chartered a new deprocessing technique by combining selective wet-etching of passivation and Inter Metal Dielectric (IMD) layers and mechanical lapping/polishing have been developed. Selective removal of passivation and IMD layers is of major importance in failure analysis of semiconductor devices. The key objective of this technique is to etch away passivation and IMD layers without attacking any metallization. This new deprocessing technique enables failure analyst to delayer by wet-etch again even those submicron devices. It avoided dry etch related problem such as selectivity, temperature control, etch rate stability, RIE grass, side wall polymer and end point detection…etc. It offers a cheaper alternative method for deprocessing when the plasma etcher is not available.

In this report our SRAM failure analysis flow based on a two metal SRAM and a six transistor cell design is presented. The basic SRAM failures inside the cell array are considered. With standard SRAM tests, the failing cells are detected and a fail bitmap with the physical location of the failing cells is generated. The SRAM failures are classified by the pattern formation of the fail cells. The main focus is on the analysis of single bit failures. In contrast to the often limited physical preparation of SRAMs, a detailed description of the electrical analysis with microprobes, especially of single bit cells, is given. The electrical cell analysis is not limited to hard fails. Soft fails are also accessible. For the different failure classes of the flow, a detailed description of the preparation and physical localization methods e.g. voltage contrast and electrical characterization methods using microprobes is given. Furthermore, analysis results are presented for the different failure classes.

The continuous scaling of memory technology drives, among other things, an increasing vertical integration. The storage capacitor of a memory cell can be formed as a deep trench into the Silicon to allow high capacitance with a minimum footprint. This paper summarizes preparation techniques especially developed for vertical dielectrics, which are used, for example for the deep trench storage capacitor and the vertical access transistor for this capacitor. The preparation methods employ mechanical polishing, focused ion beam milling and chemical etching to allow for some of the best possible inspection in SEMs and TEMs.

Low yield was reported for a non-volatile embedded memory array. In one case, the n-channel transistor was observed to exhibit single bit OFF leakage in a 32K array. In another case, there was general leakage observed between drain junctions of neighboring transistors, even though these were isolated by field oxide. The objective of the failure analysis described in this article was to characterize the electrical behavior of the leakage and determine the exact location and cause of the leakage. Focused Ion Beam was used to make electrical contact to drain regions, which lacked a contact for microprobing. Once the electrical parameters were obtained, photoemission analysis was performed with modified probes for higher spatial resolution to pinpoint the leakage path. Finally, scanning capacitance microscopy methods were used to prove the presence of the n-type depletion path. Very clear and positive confirmation of the presence of the parasitic n-type dopant was confirmed.

The repetitive energy discharge test (power cycling) is an accelerated stress test (AST) that can be used to characterize the long-term behavior of power transistors taking into account stress on customer final application. This paper describes the application of this test to an LDMOS transistor in order to optimize both design and size while preserving final reliability of the product. We will detail this reliability characterization program, emphasizing the power cycling tests performed in extreme conditions in order to reach and study physical limit of LDMOS devices. Analysis of LDMOS devices under these extreme conditions indicated evidence of metal voiding: the conditions of formation of these thermal fatigue induced voids will be discussed. The effect of major parameters like power cycling energy, ambient temperature will also be discussed. Electrical characterization of stressed devices will be presented. Finally, the results of the Transmission Electron Microscopy characterization of the metal microstructure will be discussed.

When a failure analysis (FA) involves a multiple layer structure separated by a polymeric material such as Benzocyclobutene (BCB), in a plastic package, it becomes a very challenging task to find out where the failure site is and how it failed. This is due to the fact that the chemical de-processing procedure removes BCB as well as the plastic molding compound. This paper outlines the studies carried out to determine the failure site and the root cause of the failure mechanism in a multilayer circuit and the steps taken to fix the problems. The methodology and results of this study are applicable to many other types of circuits.

Mechanical stress problems in integrated circuit devices are becoming more severe as the number of metal interconnect levels increases and new materials such as low-k dielectrics are introduced. We studied dielectric cracking in a four-level Al-Cu interconnect structure that uses hydrogen silsesquioxane (HSQ), a low dielectric constant (low-k) material. The cracks extended down through the passivation layers to the HSQ layer. For the first time we report on passivation dielectric cracks directly related to the level of residual fluorine in a plasma enhanced chemical vapor deposition (PECVD) reactor. It is shown that a silicon nitride pre-coat deposition removes fluorine (F) from the reactor ambient and prevents the dielectric cracks.

To find defects and their root cause in semiconductor devices has become more and more difficult as chip size dramatically drops. A novel method combining FIB sequential cross-sectioning and TEM is described in this paper. This combination has provided a powerful tool for defect mechanism analysis. FIB slicing through a failed cell can be controlled to a precision of 0.1 micron. Passive voltage contrast imaging with FIB enhances defect detection. After a defect is found, in-situ TEM sample is prepared with FIB milling. By putting together the series FIB images along side with the TEM images and its associated high resolution EDS data, the detailed defect formation mechanism was discovered and feedback to process engineering for process improvement.