This paper presents a novel approach in analyzing power distribution network (PDN) from a failure analysis perspective. PDNs, although technically should only have DC component, due to the nature of digital systems it powers and the way current is drawn in time and frequency domains, it is essential to look at AC component as well. AC component: impedance plays a huge role in PCB power rails and the different components (active and passive) that connect to it. Different components (i.e., voltage regulators (VR), bulk capacitors, ceramic capacitors, etc.) influence different frequency ranges. Fault isolation is the first step in ensuring the failure location is identified. A combination of near field spectrum analysis and two-port shunt impedance enables the failure analyst to isolate the component that is failing/degraded through this approach. The aim of this paper is to showcase the alternate approaches available for failure analysis of power rail/PDN failures along with their limitations.

Air-assisted liquid cooling (AALC) has emerged as a preferred cooling solution for data centers housing traditional air-cooled server racks, owing to its straightforward integration with existing infrastructure. However, the rising power demands of AI hardware (30-100kW per rack) and its variable computational loads generate unprecedented heat levels that challenge system reliability and uptime. Through long-term reliability testing of AALC systems, we identify and analyze unique failure mechanisms associated with liquid cooling implementations. This paper presents our findings on system vulnerabilities, details the failure analysis methodology, establishes root causes, and outlines the corrective measures implemented to enhance AALC system reliability in high-performance computing environments.

The intent of this paper is to present several case studies that highlight different analytical methods used to isolate short circuits within Circuit Card Assemblies (CCAs). When working with CCAs, each investigation may present its own unique challenges that can be solved utilizing a diverse toolset. This toolset does not just include test equipment but rather a catalog of methodologies and processes, which is learned through experience while leveraging how others have approached similar problems.

Board level semiconductor reliability testing (BLTT) is a crucial step in the product development life cycle of modern electronics. While the primary focus of semiconductor reliability historically has been to understand the robustness of the solder joint, there are other aspects of the semiconductor package which are also susceptible to failure after the product has been assembled. Despite its overwhelming importance, there is no one centralized resource outlining best practices for conducting BLRT across industries. Fortunately, industry standards do exist. Among them are outlines for conducting tests including temperature cycling, mechanical shock, humidity dwell among others. In this work we present a case study exploring some of the unique challenges and methods associated with conducting BLRT using mechanical shock testing. Namely, we discuss the practical challenges of conducting these tests in the presence of a constant noise source and performing die level failure analysis on components suffering from warpage while back side films (BSFs) are applied as a protective coating on the package.

Lead-free solder joints tend to be more susceptible to brittle fracture, and thus susceptible to drop-damage. Drop testing of handheld ultrasound devices revealed broken solder joints on a large inductor component. Analysis of the cracks showed a dual intermetallic compound (IMC) layer of Ni 3 Sn 4 (closest to the nickel) and (Ni,Cu) 6 Sn 5 , with the crack occurring in between the two layers. The inductor had a tinned nickel lead finish; the solder was SAC305 (a common lead-free solder comprising Sn, Ag, and Cu); and the printed circuit board (PCB) had a standard copper finish. The failure occurred very soon after manufacture and had not been enhanced by temperature cycling or aging, but it was not a time-zero failure: mechanical shocks from drops were required to propagate the crack through the joint fully. Strain measurements did not find any large strains after reflow and assembly, and no other components on the board showed cracking. There was no cracking observed at the PCB (Cu) side of the solder joint. The solution ultimately was to redesign the board, replacing the large single component with several smaller ones.