The increasing popularity of flip-chips brings new challenges to those who must perform device analysis (1). Its ability to accommodate high pin-count and high bandwidth microprocessors, DSPs and complex logic devices is increasing the demand for this technology. Conventional e-beam and mechanical probing techniques currently allow quick and efficient analysis of conventional semiconductor devices. When the surface of the device is not exposed, however, conventional analysis techniques are insufficient and new techniques must be developed. Conventional packaging technologies allow design debug and failure analysis to be performed in a relatively straightforward manner. Analysis from the topside is clearly the preferred technique when possible (2), using specially prepared engineering prototypes, but backside access for dynamic timing analysis is required when topside techniques are exhausted. The flipchip process, however, makes topside analysis impractical in most situations. There are several different techniques that are currently being used for backside analysis. These are emission microscopy (3), optical beam induced current (OBIC) (4), and a combination of software and built in self-test/scan methods (5). These techniques are valuable in helping engineers to analyze and isolate faults for functional failures. These techniques do not, however, provide precise analog waveforms which may be used to perform timing analysis on the device. A backside pulsed laser electro-optic technique for measuring internal node timing (6) has been developed for waveform acquisition. Although this technique permits acquisition of waveforms from a bi-polar device which has had its substrate thinned, it has limited application to CMOS devices, particularly in long duty cycle applications. Milling the backside of devices in order to facilitate backside waveform acquisition is considered by some researchers as a potential approach, but the authors are not aware of any published data on this subject.

We can identify various contrasts by scanning an 1.3 um laser beam from the backside of a chip and displaying current changes as brightness changes on a CRT, because the 1.3 um laser beam generates no OBIC signal and can penetrate P- Si substrate with little intensity degradation. The contrasts we have confirmed up to now are: (1) Current pass contrast at Al lines caused by OBIRCH, (2) Defect contrast at Al interconnects caused by OBIRCH, (3) Current pass contrast at a poly Si lines caused by OBIRCH, (4) Parasitic MIM (metal-insulator-metal) contrast caused by temperature dependence of MIM current, (5) Schottky-barrier contrast caused by internal photoemission.

With increasing complexity of circuit layout on the die and special packages in which the die are flipped over, failure analysis on the die front side, sometimes, can not solve the problems or is not possible by opening the front side of the package to expose the die front side. This paper discusses fault isolation techniques and procedures used on the back side of the die. The two major back side techniques, back side emission microscopy and back side OBIC (Optical Beam Induced Current), are introduced and applied to solve real problems in failure analysis. A back side decapsulation technique and procedure are also introduced. Last, several examples are given. The results indicated that the success in finding root cause of failure is greatly increased when these techniques are used in addition to the traditional front side analysis approaches.

Reducing the cell size of DRAMs in 0.35 micron and follow-on technologies requires failure analysis techniques that can analyze single storage node trench capacitors on both test sites and actual product. A combination of electrical microprobing, probeless voltage contrast and physical delayering procedures, all based on focused- ion-beam (FIB) techniques, are described. Because of precise fail localization, high resolution scanning electron microscope (SEM) imaging enables the distinction between process defects and intrinsic breakdowns of node dielectric defects. Isolated storage cells can be electrically characterized by depositing small probe pads, using FIB for contact hole milling and probe-pad deposition. To localize trench capacitors with a leakage path to the surrounding substrate, the trenches are isolated by mechanical polishing and probeless voltage contrast in the FIB tool. Failing trench capacitors can be marked in the FIB tool. Physical isolation of leaking trench capacitors can be achieved by recessing the adjacent trench capacitors, with the FIB used for milling and a subsequent wet chemical removal added for the remaining substrate material. Alternatively, trench capacitors can be inspected from the backside when stabilized by a quartz deposition on top, followed by mechanical polishing from the side and a wet chemical etching of the remaining substrate material. In both cases, the dielectric of the node trench capacitors can be inspected by high resolution SEMs and the defect areas precisely analyzed.