The photoemission microscope (PEM) is a powerful and widely used tool for location and identification of failure sites on integrated circuit (IC) chip and wafers. A PEM operating in the infrared (IRPEM) offers several advantages over systems operating in the visible part of the spectrum.. A combined PEM/IRPEM has been built having a cooled (77K) mercury cadmium telluride (MCT) focal plane array (FPA) sensitive in the range 800 to 2500 nm, an intensified charge coupled device (CCD) camera sensitive in the range 350 to 900 nm and a conventional, colour CCD camera. A cooled filter wheel enables the user to select the spectral range of the FPA. Direct comparison of photoemission images obtained in the IR and visible parts of the spectrum is straightforward, while the colour camera permits easy navigation around the device and facilitates probing of wafers. Comparing the sensitivity of the IRPEM with a conventional PEM camera (GEN III intensifier) indicates that for forward bias emission and NMOS emission the IRPEM is approximately 500 times more sensitive. Applications of the system to failure analysis in ICs, sensor devices and electronics packaging are described.

Light emission and heat generation of Si devices have become important in understanding physical phenomena in device degradation and breakdown mechanisms. This paper correlates the photon emission with the temperature distribution of a short channel nMOSFET. Investigations have been carried out to localize and characterize the hot spots using a spectroscopic photon emission microscope and a scanning thermal microscope. Frontside investigations have been carried out and are compared and discussed with backside investigations. A method has been developed to register the backside thermal image with the backside illuminated image.

Today’s process technology requires ever-increasing number of metal layers to meet the power and layout needs of modern products. These advances have rendered many of the conventional fault isolation (FI) methods from the front side of the die obsolete. The flip-chip package not only brings about the need to localize defects at die level through the Si substrate, but also introduces the need to isolate new defects at the package level. Recently, an infrared (IR) emission microscope which utilizes the cryogenically cooled HgCdTe (MCT) imaging array having spectral response of 0.8μm- 2.5μm, for near IR emission detection was developed. This system supersedes the conventional CCD based emission microscope with a spectral response of 0.4 μm-1.1μm. Since spectral detection extends into the thermal spectral region, it also offers an added advantage of detecting thermal spots on the die and flip-chip package where liquid crystal hot spot detection method is not possible. This article is an account of the use of the Mercury-Cadmium- Telluride based IR detector for “real life” failures. The article will demonstrate key features of the system as well as several FI examples. Both emission and thermal detection modes will be discussed. The authors will present several problems, including melted die bumps and package copper trace shorts, that could not be detected through conventional failure analysis (FA) methods, such as liquid crystal or front side emission microscopy. The MCT detectors increased sensitivity and backside navigation capabilities coupled with backside die preparation has proven itself an indispensable FA tool in the high volume manufacturing environment.

Silicon microsurgery, also known as on-silicon circuit editing, has evolved into a critical capability for the ramp-up of a new microprocessor or complex integrated circuit (IC) from tapeout to production. The ability to perform edits directly on a packaged device serves two major purposes during a product’s ramp. The first is to perform in-situ verification of logic and timing related design changes, and the second is to provide engineering samples to enable further debug for system and tester level validation. In both cases, sample generation using silicon microsurgery technology can be performed in a fraction of the time it would take to tapeout a new mask layer and generate samples through the fabrication process. Silicon microsurgery techniques are also employed to assist with failure analysis. For this application, these techniques are applied to help isolate a stuck-at fault or open on a failing node. This is done by bi-passing the failure point, through signal rerouting or by performing isolation cuts to further localize the defect. This paper will review several advanced siliconmicrosurgery edit applications and supporting technologies, microsurgery RC material properties, and finally some results from 0.25 and 0.18 micron technologies.

Recent advances in integrated circuit technologies and in interconnect methodologies to external electronics have made it extremely difficult to conduct failure analysis from the top side of the die (1,2). Therefore analysis techniques are being developed that allow analysis from the backside of the die. The first step in this process involves gaining access to the back of the die through the packaging material. Most backside analysis techniques require that the die then be thinned and polished. This paper describes specialized equipment and procedures to meet those requirements. The equipment is relatively inexpensive compared to other approaches.

Backside emission microscopy on heavily doped substrate materials was analyzed from the viewpoint of optical absorption by the substrate and sample preparation technique. Although it was widely believed that silicon is transparent to infrared (IR) radiation, we demonstrated by using published absorption data that silicon with doping levels above 5 x 10 18 cm -3 is virtually opaque, leaving only a narrow transmission window around the energy bandgap. Because the transmission depends exponentially on the thickness of die, thinning to below 100µm is shown to be required. Even an advanced IR sensor such as HgCdTe would find little light to detect without thinning the die. For imaging the circuit, an IR laser-based system produced poor images in which the diffraction patterns often ruined the contrast and obscured the image. Hence, a precise, controlled die thinning technique is required both for emission detection and backside imaging. A thinning and polishing technique was briefly described that was believed to be applicable to most ceramic packages. A software technique was employed to solve the image quality problem commonly encountered in backside imaging applications using traditional microscope light source and a scientific grade CCD camera. Finally, we showed the impact of die thickness on imaging circuits on a heavily doped n type substrate.

The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness of traditional micro-surgery. Advancements in FIB technology and its application now allow access to the circuitry from the backside through the bulk silicon. In order to overcome the problem of imaging through thick silicon, a microscope with Infra Red (IR) capability has been integrated into the FIB system. Navigation can now be achieved using the IR microscope in conjunction with CAD. The integration of a laser interferometer stage enables blind navigation and milling with sub-micron accuracy. To optimize the process, some sample preparation is recommended. Thinning the sample to a thickness of about 100 µm to 200 µm is ideal. Once the sample is thinned, it is then dated in the FIB and the area of interest is identified using the IR microscope. A large hole is milled using the FIB to remove most of the silicon covering the area of interest. At this point the application is very similar to more traditional FIB usage since there is a small amount of silicon to be removed in order to expose a node, cut it or reconnect it. The main differences from front-side applications are that the material being milled is conductive silicon (instead of dielectric) and its feature-less and therefore invisible to a scanned ion beam. In this paper we discuss in detail the method of back-side micro-surgery and its electron device performance. Failure Analysis (FA) is another area that has been severely limited by flip-chip packaging. Localized thinning of the bulk silicon using FIB technology offers access to diagnosing failures in flip-chip assembled parts.

Laser microchemical etching systems provide enhanced through-wafer IR viewing and provide access for focused ion beam (FIB) tools and e-beam testers on flip-chip packaged die [1]. In demanding applications, laser etching is directed at rates of 100,000 cubic micrometers per second and must be stopped within 10 to 15 micrometers (thickness remaining) of the active flip-chip circuit. In cases where the initial die thickness is known, the laser process is sufficiently reproducible and system depth of focus is sufficiently narrow to place the laseretched floor within an accuracy of about plus or minus 5 micrometers relative to the initial surface of the die. However, greater accuracy is often desired to minimize FIB etch time. In addition, the laser step is often proceeded by a mechanical thinning operation on the die. This mechanical process introduces an uncertainty in initial part thickness, as well as part wedge and bowing. In this paper we describe an optical beam induced current (OBIC) method for accurate closed-loop endpointing with direct reference to the active device surface on the flipped die. The method relies on an exponentially increasing current that is induced by the laser as the device is thinned. Because of the strong absorption of the silicon bulk at visible wavelengths, the signal is sensitive to submicrometer thickness changes and, hence, may be used to stop the laser etching process with high accuracy at the desired 10 to 15 micrometer distance from the active circuit. The new technique has been studied on commercially available devices and shown to be insensitive to localized device junction density. Hence, endpointing is not highly dependent on the circuit design or exact placement of circuit elements. We outline the substrate and circuit properties that are most relevant to accurate implementation of the technique. The laser-etch process dependency of the OBIC signal has also been characterized. Simple high-speed closed loop electronics have been developed in order to apply the method for in situ endpointing New failure analysis/circuit debug techniques, including spectroscopic photoemission and picosecond time-resolved methods rely on observation of weak optical signals through the wafer. These would optimally be viewed though a remaining silicon thickness of a few micrometers or less. The limits of the OBIC endpointing method have been explored for the high-speed preparation of ultra thin local viewing windows in support of these new techniques.

This paper describes a new technique for identifying defects on integrated circuit. This technique detects the noise content in light emitted from defect sites. The purpose of this technique is to determine which of many light emission sites represent a defect and which represent normal devices. It reports the first phase of studies to evaluate the feasibility and potential effectiveness of this technique. The feasibility of this technique has been demonstrated by simultaneously monitoring electrical noise and the noise in the light emitted from a gallium arsenide light emission diode (LED) and a bipolar transistor. The paper will present the methodology and apparatus used to detect and analyze the noise in light emission.

The advent of Flip Chip and other complex package configurations and process technologies have made conventional failure analysis techniques inapplicable. This paper covers the ways in which conventional techniques have been modified to meet the FA challenges presented by these new devices – specifically, by forcing analysis to be done from the backside of the device. Modifications to the traditional FA process steps, including new sample preparation methods, changes in hardware, and alterations to physical failure analysis processes are described. To demonstrate the use of backside analytical approaches, some examples of applications and a case study are also included.

A noninvasive backside probe of integrated circuits has been developed. This new probe can diagnose at-speed failures, stuck faults, and other defects. Because it is a highly parallel imaging technique, faults may be isolated which are difficult to locate by other methods. This optical technique has been named “PICA”, for picosecond imaging circuit analysis. PICA relies on the fact that an FET in a CMOS circuit emits a picosecond pulse of light each time the logic gate changes state. The source of this emission is explained. The PICA technique, which combines optical imaging of the emission with picosecond time-resolution, is described. Because of the imaging, time-resolved emission data is acquired for many transistors in parallel. The use of the emission for failure analysis and AC characterization of integrated circuits is demonstrated. Because the emission can be detected from either the front or back side of the chip, it can be used for both front and back side analysis.