Several considerations related to the implementation of the thermal laser stimulation method (OBIRCH, TIVA) in a failure analysis laboratory will be discussed. At the CNES (French Space Agency), we implemented this method on a dual system which includes an emission microscope and a laser-scanning microscope. The amplifier used for amplifying the weak voltage or current variations caused by thermal laser stimulation was shown to be a key factor. The design of such a low noise, high gain and fast voltage amplifier is described. From a 3D finite element ANSYS model of the thermal laser stimulation effect combined with three practical case studies we show that thermal laser stimulation is a rapid and precise method for localizing metallic short type faults in ICs. In order to interpret the thermal laser stimulation signal, a simple CMOS inverter model is also presented.

The unique physical phenomenon of photon emission from a variety of defects in ICs has long been exploited for failure analysis. This method provides a fast non-destructive inspection method for failure localization. Several functional failures have a distinctive emission signature that allows functional analysis of the design. The transition to flipchip packaging accelerated the use of Infrared Focal Plane Arrays (IR FPA) such as MgCdTe (MCT). It has been proven that systems that incorporate MCT arrays demonstrate higher sensitivity for emissions in comparison to the traditional Si CCDs; usually the higher sensitivity is compromised with inferior resolution. In this work we will review and demonstrate the optical limitations involved with the use of an MCT camera, yet we shall show a calibration procedure carried out by the analyst to bypass these limitations. By calibrating typical emissions, generated by typical functional defects, we generate calibration curves, which supply a fast reference for detection of the defective transistor, and the correlated current that results from the defect. The calibration of the array response is crucial for evaluation of its sensitivity. It will also enable a clear distinction between emissions, which correlate to small or negligible current flows, and emissions that correlate to significant current flows. We also classify logic failures that lead to emissions, and estimate the level of emission anticipated from these failures.

The paper details a critical innovation for scaling optical probing to access the small feature sizes on advanced silicon process technologies. By using the liquid immersion principle to increase the numerical aperture of the microscope objective, a focused laser spot size of 0.50 µm is achieved for the first time. The liquid immersion objective is the first known application of the immersion principle to backside probing. This system improvement allows optical probing to be used in geometrically scaled processes that would not be accessible without it, and thus will extend the usefulness of laser probing for at least one more generation.

Thermal beam induced techniques such as Thermally Induced Voltage Alteration (TIVA), Seebeck Effect Imaging (SEI) [1] and Optical Beam Induced Resistance Change (OBIRCH) [2] have been used for localization of reliability related faults in integrated circuits over the last few years. In this paper, we describe several approaches to optimize the detection of thermal beam induced phenomenon. In the first method, we have improved control of the laser scanning system to define a specific dwell time at each pixel. Secondly, we utilized a voltage source in series with an inductor to detect the induced voltage changes as the laser is scanned across the device. Finally, we employed a pulsed laser and a lock-in signal processing technique to increase the signal-tonoise ratio.

An increasing number of analysis techniques requires access to the backside silicon of a functional device. For backside sample preparation of packaged devices, CNC milling tools can perform both package opening and circuit preparation. They offer good versatility in terms of type and size of packages – from ceramic to exotic plastic molding. They are suited for precise silicon thinning as well as polishing. Finally, the automation and software control of the process offer good reproducibility of chip opening and preparation. For some applications, the silicon substrate needs to be thinned as closely as possible to the circuitry with a uniform thickness (less than 100 microns). Bent silicon surfaces are challenging for backside sample preparation. This is the case of C4 packages or large plastic TSOP packages. Conventional approaches would cut off the top of the bent surface. From small flat surface to large bent silicon dies, we will detail our technique for thinning silicon to a uniform thickness with extreme precision. Finally, we will characterize the final surface roughness which plays an important role in backside techniques.

Emission microscopy and thermal laser stimulation (OBIRCH, TIVA) are two key methods for backside failure analysis. They are both dedicated for localizing current leakage faults in ICs. The complementary relationship of these two techniques is illustrated through six practical case studies. Thermal laser stimulation was able to precisely and directly localize defects such as shorts in the IC’s metallic elements that where not readily detectable by emission microscopy. The case studies also illustrate the ability of thermal laser stimulation to detect and physically localize defects in the IC’s polysilicon layers and silicon substrate.

In this paper a method is presented to remove the silicon substrate from the back of a CMOS chip altogether, whilst leaving gate oxide and silicide intact. This is achieved by grinding the chip until it becomes transparent and then selectively etching the remaining silicon away. The procedure developed is very fast: A 50 mm2 die can be prepared in under an hour, with the gate and silicide of every transistor intact. The method is especially valuable when front-end process features need to be examined over a large sample area. Information can thus be gained with less effort than by using front side deprocessing or cross sections. Several case studies are used to illustrate the effectiveness of the technique and its benefits over deprocessing from the front. These include accurate measurements of gate length (+/- 2 nm) over the entire chip in a 0.18 µm CMOS technology, and applications to investigation of silicide formation.

Two novel techniques to identify continuity failures in multi-layer substrates of flip-chip package are discussed. The first technique uses the custom designed and fabricated Package Substrate Probe Fixture (PSPF™). The fixture eliminates the traditional method of soldering directly to the package solder balls. This ensures that failures are not heat cured and the solder ball as well as the Ball Grid Array (BGA) pad are not detached from the package substrate during physical analysis. Also employed are beam-based systems that include both Focused Ion Beam (FIB) and Electron-beam (Ebeam) to detect Capacitive Coupling Voltage Contrast (CCVC) images. Voltage contrast imaging augments traditional optical inspection techniques using bright and dark field microscopy.

The use of an antireflection coating for backside semiconductor failure analysis is discussed. The process of selecting an appropriate coating is described. Several known coatings are also described in regards to imaging quality, material properties, and the benefits to device analysis applications.

This paper presents a comparative study of backside sample preparation techniques with applicability to conventional as well as flip chip package types. We will cover mechanical (grinding and milling tools), chemical (wet and dry chemistries) and other approaches such as laser ablation. Backside sample preparation is very challenging. The preparation process flow starts with decapsulation of the ceramic or plastic package, continues with the die paddle removal, silicon thinning and finishes with silicon polishing. The techniques involved include mechanical, chemical and other novel approaches for ceramic and plastic package. Today, only CNC milling can cover the whole process for almost any kind of packages. Nevertheless, photo ablation is a rising technology for package decapsulation. In addition, chemical wet etch can be used to perform silicon thinning and polishing. We will illustrate the complexity of the process through examples. The first one is a ceramic package where the main issue is the hardness of ceramic. The second one is a TSOP package where the main challenge is the chip scaled package. Both will be observed through the IR emission microscope to demonstrate the efficiency of the preparation.

The need for failure analysis from the backside of the die has introduced new challenges in device analysis applications. Standard silicon based detectors are no longer as efficient due to the absorption of emission signals by the silicon substrate, which is now in the optical path between the device and the detector. The emergence of infrared detectors has offered a solution since emissions in this regime are not attenuated. This paper will describe a comparison made between a silicon detector and two of the most common IR detector materials.

A back side failure analysis flow has been developed in order to enable failure analysis of flip-chip, lead-on-chip dies and within multi-metal-level dies. A combination with frontside failure analysis methods is possible too. The back side flow consists of stepwise bulk silicon removal, electrical and physical failure analysis methods. Four different methods for bulk silicon thinning in order to localize electrical defects using PEM are compared. A method to remove the bulk silicon after PEM analysis to expose the gate oxide level of a die has been developed. Different back side applications like physical analysis of gate oxide defects, passive voltage contrast and microprobing with an AFM tip for detection of interrupts within conductive interconnects are described.

Optical probing using the Schlumberger IDS-2000 and other infrared-based analysis techniques have proved to be critical in the debug and analysis of flip-chip-packaged microprocessors. During probing, processors are operating with test patterns that generate a large amount of power. This article demonstrates a method for dissipating the generated heat based on a diamond window-based transparent heat spreader. This method controls the microprocessor temperature to a high degree of stability, and reduces thermal gradients across the die. Waveform results are excellent, and the transparent heat spreader provides a path for optical probing to be applied to the entire range of integrated circuit applications. The discussion covers cooling system requirements, and standard configuration specifications, and shows how the transparent heat spreader technique is effective for probing high power microprocessors.

A new ultra-short pulse laser ablation based backside sample preparation method has been developed. This technique is contact-less, non-thermal, precise, repetitive and adapted to each type of material present in IC packages. Backside preparation examples are presented on a conventional DIL plastic package, on a TSOP plastic package with an oversized silicon die, on a DIL ceramic package and on a CCD device. Feasibility of silicon thinning using laser ablation is also discussed.

The migration of microprocessor packaging from wire bond to flipchip technology in silicon "microsurgery" posed some challenges to on-chip circuit edit. The physical debug process through the backside silicon substrate was proposed as the common solution. The focus of this article is on step 2 of this process, namely the milling of large trenches over the edit area. Laser Chemical Etcher (LCE) was commonly used for this task. This article presents an alternative technique based on plasma dry etch process which consists of three steps: photolithography, plasma etching, and acoustic polishing. A detailed description of each step is provided, along with the details of experiments that were conducted for process optimization. The technique was successfully demonstrated in the preparation for backside FIB editing. However, the success rate of the proposed method is still lower than the LCE but this method can serve as a reliable backup process for the LCE.

The move towards flip-chip type packaging has produced significant obstacles for failure analysis. One such obstacle is the breakdown of traditional techniques for failure isolation via thermal mapping, typically used to isolate short circuits and leakage paths. This paper describes the application of near infrared (IR) phase-contrast techniques to allow highly sensitive, ~ 10mK, thermal mapping for backside failure analysis.