In their daily work, engineers in semiconductor Failure Analysis (FA) laboratories generate numerous documents, recording the tasks, findings, and conclusions related to every device they handle. This data stores valuable knowledge for the laboratory that other experts can consult, but being in the form of a collection of documents pertaining to particular devices and their processing history makes it difficult if not practically impossible to find answers to specific questions. This paper therefore proposes a Natural Language Processing (NLP) solution to make the gathering of FA knowledge from numerous documents more efficient. It explains how the authors generated a dataset of FA reports along with corresponding electrical signatures and physical failures in order to train different machine-learning algorithms and compare their performance. Three of the most common classification algorithms were used in the study: K-Nearest Neighbors (kNN), Support Vector Machines (SVM), and Deep Neural Networks (DNN). All of the classification models produced were able to capture patterns associated with different types of failures and predict the causes. The outcomes were best with the SVM classifier and all classifiers did slightly better in regard to physical faults. The reasons are discussed in the paper, which also provides suggestions for future work.

Lock-In Thermography is an established nondestructive method for analyzing failures in microelectronic devices. In recent years, a major improvement made it possible to acquire time-resolved temperature responses of weak thermal spots, greatly enhancing defect localization in 3D stacked architectures. One limitation, however, is in the method used to determine defect depth, which is based on the numerical estimation of the delay between excitation and thermal response inferred from the value of the lock-in phase. In structures where the region between the origin of the defect and sample surface is partially or fully transparent to infrared signals, interference between radiated and conducted signal components largely falsifies the phase value on which the classical depth estimation relies. In the present study, blind source separation based on independent component analysis was successfully used to separate interfering signal components arising from direct thermal radiation and conduction, resulting in a precise estimation of the defect depth.

This paper evaluates several approaches for automating the identification and classification of logos on printed circuit boards (PCBs) and ICs. It assesses machine learning and computer vision techniques as well as neural network algorithms. It explains how the authors created a representative dataset for machine learning by collecting variants of logos from PCBs and by applying data augmentation techniques. Besides addressing the challenges of image classification, the paper presents the results of experiments using Random Forest classifiers, Bag of Visual Words (BoVW) based on SIFT and ORB Fully Connected Neural Networks (FCN), and Convolutional Neural Network (CNN) architectures. It also discusses edge cases where the algorithms are prone to fail and where potential opportunities exist for future work in PCB logo identification, component authentication, and counterfeit detection. The code for the algorithms along with the dataset incorporating 18 classes of logos and more than 14,000 images is available at this link: https://www.trusthub.org/#/data .

In the NAND flash manufacturing process, thousands of internal electronic fuses (eFuse) are tuned in order to optimize performance and validity. In this paper, we propose a machine learning optimization technique that uses deep learning (DL) and genetic algorithms (GA) to automatically tune eFuse values. Using state-of-the-art triple-level cell (TLC) V-NAND flash wafers, we trained our model and validated its effectiveness. Based on the findings of the evaluation and production data, the proposed optimization technique can reduce total turnaround time (TAT) by 70% compared with manual eFuse tuning.

Fault analysis is a complex task that requires engineers to perform various analyses to detect and localize physical defects in semiconductor devices. The process is knowledge intensive and must be precisely documented. In order to ensure unambiguous documentation, engineers must agree on a clearly defined terminology specifying methods, tools, physical faults and their electrical signatures among other things, and it must be stored in a way that is usable for both engineers and software. One possible solution to this challenge is to formalize domain knowledge as an ontology, a knowledge base designed to store terminological definitions. This paper discusses the development of an ontology for electronic device failure analysis that uses a logic-based representation. The latter ensures that terms are interpreted the same way by engineers and software systems, facilitating the automation of tasks such as text classification, information retrieval, and workflow verification.