Using a laser to purposely damage (or zap) a static random-access memory (SRAM) bitcell for bitmap validation purposes is a well-established technique. However, the absence of visible damage in FinFET SRAM cells, amongst other things, makes precision zapping in these devices more difficult. In this paper, we describe system enhancements and a modified workflow for bitmap validation of these devices using precision, near-infrared (NIR) laser-induced damage. We also explore the use of laser perturbation and non-precision zapping options. Examples are provided.

The visible approach of optical Contactless Fault Isolation (VIS-CFI) serves the perspective of application in FinFET technologies of 10 nm nodes and smaller. A solid immersion lens (SIL) is mandatory to obtain a proper resolution. A VISCFI setup with SIL requires a global polishing process for sub-10 µm silicon thickness. This work is the first to combine all these necessary components for high resolution VIS-CFI in one successful experiment. We demonstrate Laser Voltage Imaging and Probing (LVI, LVP) on 16/14 nm technology devices and investigate a focus depth dependence of the LVI/LVP measurement in FinFETs.

This paper demonstrates a breakthrough method of visible laser probing (VLP), including an optimized 577 nm laser microscope, visible-sensitive detector, and an ultimate-resolution gallium phosphide-based solid immersion lens on the 10 nm node, showing a 110 nm resolution. This is 2x better than what is achieved with the standard suite of probing systems using typical infrared (IR) wavelengths today. Since VLP provides a spot diameter reduction of 0.5x over IR methods, it is reasonable, based simply on geometry, to project that VLP using the 577 nm laser will meet the industry needs for laser probing for both the 10 nm and 7 nm process nodes. Based on its high level of optimization, including high resolution and specialized solid immersion lens, it is highly likely that this VLP technology will be one of the last optically-based fault isolation methods successfully used.

LVx, a workhorse in many failure analysis laboratories, consists of laser voltage imaging (LVI) and laser voltage probing. Laser voltage tracing (LVT) eliminates the inherent restrictions bestowed by LVI and reduces the need for costly probing. It monitors a distinct feature of the test pattern and creates a corresponding signal map. This weapon in the LVx arsenal significantly decreases debug time and will prove as invaluable as LVI. Beginning with an overview of the limitations of traditional LVx, this paper provides information on the process steps, experimental setup, and applications of LVT. LVT introduces a new approach to monitoring LVx signals. The most obvious LVT application is debugging problematic peripheral NAND circuitry.

In this work, we demonstrate the effectiveness of deconvolution algorithms in improving the spatial resolution of time-integrated emission images from integrated circuits. A mathematical model of the Point Spread Function (PSF) encompassing both the optical system and the imaging detector properties is used for the deconvolution process. Tuning of the PSF parameters is achieved through the minimization of dedicated cost functions that optimize image resolution while suppressing artifacts in the deconvoluted images. The optimized PSF is then used in both the Lucy-Richardson (L-R) and blind deconvolution algorithms. Results from 32 nm and 14 nm SOI devices show that the deconvolution process significantly improves spatial resolution of time-integrated emission images, pushing their resolution beyond the diffraction limit of Solid Immersion Lenses (SILs).

An ARC solution that can be used to improve backside imaging for backside photoemission microscopy applications is presented in this paper. Zinc Oxide (ZnO) -based thin films used as ARCs are deposited at the backside of the failing units through a simple and low cost spray pyrolysis technique. An improvised set-up, composed of an atomizer and a hot plate, is used in the experiment. The paper provides evidence of acceptable process repeatability and demonstrates that the technique and the material have important applications in the field of failure analysis. Furthermore, it shows that the application of ARC resulted in better defect localization. The location of the defect is easily been determined upon doing frontside inspection - to - backside image comparison on the deposited unit. By using high kV ion beam passive voltage contrast (PVC) and angled cut focused ion beam (FIB) cross section, we are able to isolate further and show the nature of the defect at the failing block.

Driven by the need for higher test-compression, increasingly many chip-makers are adopting new DFT architectures such as “Extreme-Compression” (XTR, supported by Synopsys) with on-chip pattern generation and MISR based compression of chain output data. This paper discusses test-loop requirements in general and gives Advantest 93k specific guidelines on test-pattern release and ATE setup necessary to enable the most established EFA techniques such as LVP and SDL (aka DLS, LADA) within the XTR test architecture.

We present a new method of imaging integrated circuits (ICs) using a dual-laser scanning confocal microscope. In this method we introduce physical and/or functional changes to the integrated circuit using the first ‘pump’ laser and then image the response of the circuit using the second ‘probe’ laser. We propose several novel applications of this imaging method. Specifically, we show how to image the flow of injected charge carriers and use the derived images to improve the resolution of material interfaces. We also show how to image changes to activity and laser voltage-probed waveforms and use the information to discover electrical connections between logic cells.

By inducing two-photon absorption within the active layer of a 28nm test chip, we demonstrate nonlinear laser-assisted device alteration and single-event upsets by temporarily perturbing the timing characteristics of sensitive transistors. Individual qualitative and quantitative evaluations are presented for both techniques, with lateral resolutions demonstrated with sub-100nm performance. A simplistic signal response rate comparison analysis of these two technologies is also presented.

In this paper, we present a Superconducting Nanowire Single Photon Detector (SnSPD) system and its application to ultra low voltage Time-Resolved Emission (TRE) measurements (also known as Picosecond Imaging Circuit Analysis, PICA) of scaled VLSI circuits. The 9 µm-diameter detector is housed in a closed loop cryostat and fiber coupled to an existing Emiscope III tool for collecting spontaneous emission light from the backside of integrated circuits (ICs) down to a world record 0.5 V supply voltage in a few minutes.

While transistor gate lengths may continue to shrink for some time, the semiconductor industry faces increasing difficulties to satisfy Moore’s Law. One solution to satisfying Moore’s Law in the future is to stack transistors in a 3-dimensional (3D) formation. In addition, the need for expanding functionality, real-estate management and faster connections has pushed the industry to develop complex 3D package technology which includes System-in-Package (SiP), wafer-level packaging, through-silicon-vias (TSV), stacked-die and flex packages. These stacks of microchips, metal layers and transistors have caused major challenges for existing Fault Isolation (FI) techniques. We describe in this paper innovations in Magnetic Field Imaging for FI which have the potential to allow 3D characterization of currents for non-destructive fault isolation at every chip level in a 3D stack.

High speed, time-resolved, thermoreflectance imaging is a novel way to locate defects or regions of potential failures in microelectronic devices. This paper reports on our thermoreflectance technique for dynamic imaging of circuit temperature distributions. This transient imaging method is based on a precise electrical lock-in technique with image processing similar to an old fashioned animation movie. An ordinal shutter speed camera is used in conjunction with an illumination LED that is pulsed for sampling the temperature distribution. This paper presents the method and gives a description of the system hardware. A theoretical comparison to lock-in thermography, which is based on infrared emission imaging, will be given. Limitations of thermoreflectance and the driving factors for spatial and time resolution will be discussed. Finally, we highlight and provide examples of near infrared (NIR) wavelength imaging, to enable both through-silicon thermal imaging and emission imaging in the same system. The combination of these two techniques is expected to enable hotspot temperatures and any anomalous emission sites to be correlated, hopefully leading to a better understanding of the nature of the defect.

Aplanatic solid immersion lens (SIL) microscopy is required to achieve the highest possible resolution for next generation silicon IC backside inspection and failure analysis. However, aplanatic SILs are susceptible to spherical aberration introduced by substrate thickness mismatch. We have developed a wavefront precompensation technique using a MEMS deformable mirror and demonstrated an increase in substrate thickness tolerance in aplanatic SIL imaging. Good agreement between theory and experiment is achieved and spot intensity increases by at least a factor of two to three are demonstrated for thicknesses deviating several percent from ideal. This technique is also capable of fixing aberrations due to SIL fabrication, off-axis imaging and refractive index mismatch.

Recently, a new approach for isolation of open faults in integrated circuits (ICs) was developed. It is based on mapping the radio-frequency (RF) magnetic field produced by the defective part fed with RF probing current, giving the name to Space Domain Reflectometry (SDR). SDR is a non-contact and nondestructive technique to localize open defects in package substrates, interconnections and semiconductor devices. It provides 2D failure isolation capability with defect localization resolution down to 50 microns. It is also capable of scanning long traces in Si. This paper describes the principles of the SDR and its application for the localization of open and high resistance defects. It then discusses some analysis methods for application optimization, and gives examples of test samples as well as case studies from actual failures.

Space Domain Reflectometry (SDR) is a newly developed non-destructive failure analysis (FA) technique for localizing open defects in both packages and dies through mapping in space domain the magnetic field produced by a radio frequency (RF) current induced in the sample, herein the name Space Domain Reflectometry. The technique employs a scanning superconducting quantum interference device (SQUID) RF microscope operating over a frequency range from 60 to 200 MHz. In this paper we demonstrate that SDR is capable of locating defective micro bumps in a flip-chip device.

Electro-optical terahertz pulse reflectometry (EOTPR) was introduced last year to isolate faults in advanced IC packages. The EOTPR system provides 10μm accuracy that can be used to non-destructively localize a package-level failure. In this paper, an EOTPR system is used for non-destructive fault isolation and identification for both 2D and 2.5D with TSV structure of flip-chip packages. The experimental results demonstrate higher accuracy of the EOTPR system in determining the distance to defect compared to the traditional time-domain reflectometry (TDR) systems.

The standard Ga focused ion beam (FIB) technology is facing challenges because of a request for large volume removal. This is true in the field of failure analysis. This article presents the first combined tool which can fulfill this requirement. This tool offers the combination of a high resolution scanning electron microscope (SEM) and a high current FIB with Xe plasma ion source. The article focuses on failure analysis examples and discusses the different steps of extra large cross sections (deposition of protective layer, rough milling, and polishing). Several applications of the novel Xe plasma FIB/SEM instrument are shown with respect to the failure analysis. The performance of the instrument is tested and discussed in comparison to gallium liquid metal ion source FIB systems. Results show that the Xe plasma FIB offers much higher milling rate, greatly reducing the time necessary for many failure analysis tasks.

Interactive electrical endpoint detection when thinning conductive and capacitive materials opens the door to approaching a suspect site in an IC without relying on the traditional iterative approach. Controlled approach of embedded conductors in insulators (packages) as well as controlled die thinning with submicron control will be shown, allowing safe approach to the desired feature without overshoot.

In this paper, we evaluate a novel, position-sensitive, singlephoton detector with enhanced Near InfraRed (NIR) sensitivity [1-3] for taking 2D Time Resolved Emission (TRE), also known as Picosecond Imaging for Circuit Analysis (PICA), in future low voltage SOI technologies. In particular, we will investigate and quantify the sensitivity of two generations (Gen. I and Gen. II) of PICA cameras by Hamamatsu Photonics as a function of the power supply voltage on an IBM 45 nm SOI test chip. Additionally, we will compare the results to the performance obtained with an InGaAs Single Photon Avalanche Diode (SPAD) from DCG Systems [4]. Finally we will show a case study and an advanced analysis and localization technique that takes advantage of the 2D capability of the camera.

A variety of EFA techniques have been deployed to improve scan chain failure isolation. In contrast to other laser techniques, modulation mapping (MM) does not require electrically perturbing of the device. Beginning with a review of MM and continuous-wave (CW) probing as well as shift debug using MM, this paper presents three case studies involving scan chains with subtle resistive and leakage failure mechanisms, including transition, bridge, and slow-to-rise/fall failures, using a combination of these techniques. Combining modulation mapping with laser probing has proven to be a very effective and efficient methodology for isolating shift defects, even challenging timing-related shift defects. So far, every device submitted for physical failure analysis using this workflow has led to successful root cause identification. The techniques are sufficiently non-invasive and straightforward that they can be successfully applied at wafer level for volume, yield-oriented EFA.