In this paper, we present the first prototype of a Scanning Time-Resolved Emission (STRE) system consisting of a high-sensitivity, low-noise, and low-jitter single-point Superconducting Single-Photon Detector (SSPD) combined with a specialized scanning head of a Laser Scanning Microscope (LSM). This idea was first proposed in late 2006 [1] but required the right combination of detector, customization, and collaboration with a tool vendor to get to fruition. It should be understood that this is still a prototype system under development and significant improvements in acquisition time, resolutions, and performance are expected in the near future. In this paper, we will also present the first preliminary results acquired using a test chip fabricated in 32 nm SOI.

Limited spatial resolution and low signal to noise ratio are some of the main challenges in optical signal observation, especially for photon emission microscopy. As dynamic emission signals are generated in a 3D space, the use of the time dimension in addition to space enables a better localization of switching events. It can actually be used to infer information with a precision above the resolution limits of the acquired signals. Taking advantage of this property, we report on a post-acquisition processing scheme to generate emission images with a better image resolution than the initial acquisition.

Post-fault isolation layout net trace and circuit analysis based on abnormal hotspots is a critical step because it directly impacts the outcome of failure analysis. In this work, we review current commercial net tracing solutions in terms of their strengths and drawbacks. As an enhancement, a new net methodology that enables automation and the capability to execute tracing beyond first-level transistors is introduced. This approach could potentially eliminate manual net tracing and significantly improves the overall failure analysis turnaround time.

High core-Vdd overvoltage latchup margins in CMOS ICs are required to enable many reliability screens (e.g., DVS and HTOL testing). We introduce an efficient way to isolate defects that degrade these margins using PEM and 1064/1340 nm CW laser-stimulation. Current pulses from a current amplifier are used to rapidly charge and discharge the DUT power rail to repetitively ramp Vdd to (or near) the latchup threshold. The characteristic drop in Vdd when latchup is induced is used to generate a latchup flag for laser-stimulation mapping. Latchup events are automatically terminated and latchup durations are minimized, leading to high stability/repeatability of the technique. Isolations down to the cell level were successfully performed in sub-14 nm FinFET test vehicles. This level of isolation is unmatched and this is the first reported use of thermal laser stimulation for latchup investigations. In one provided example, the latchup trigger was isolated to FET based decoupling capacitors (decaps) widely used as fill.

High numerical aperture (NA) laser scanning for fault localization requires the use of special lenses aimed at creating a tightly focused laser spot within an integrated circuit. Typically, extrinsic solid immersion lenses are employed that optimize the refraction at the air-silicon surface. In this feasibility study we investigate with both simulations and experiments the use of integrated diffraction lenses for high-NA imaging. We take the limit to ultrathin silicon and discuss the implications for the lens design and performance.

In this paper, an automated contactless defect analysis technique using Computer Vision (CV) algorithms is presented. The proposed method includes closed-loop control of optical tools for automated image collection, as well as advanced image analysis methods to improve image quality and detect potential defects. As an example, the technique was successfully used to identify delamination defects along the perimeter of a large test chip.

Combinational logic analysis (CLA) using laser voltage probing allows studying standard cells such as NOR or NAND gates as a whole, instead of individual transistors. The process involves building a reference library of laser probing (LP) waveforms and comparing them to signals from the real device. While CLA has greatly increased the success rate and turn-around time for LP, there are difficulties in signal interpretation. This is partly due to the lack of precise understanding of the laser interaction area and probe placement and partly due to difficulties identifying the correct logic states in the waveform. In this work, we have significantly improved the CLA process by first predicting the shape of the waveform based on laser interaction with the target circuitry and second, implementing an automated pattern search algorithm to further increase the speed and reliability of CLA using LP.

We present the first experimental demonstration of stuck-at scan chain fault isolation through the exploitation of Single Event Upsets (SEU) in a Laser-Induced Fault Analysis (LIFA) system. By observing a pass/fail flag, we can spatially map all flops after a defect in a failing scan chain through induced SEU sites produced by a fiber-amplified 25 ps 1064 nm diode laser. In addition, a custom fault isolation methodology is presented in which the result highlights only the first working flop immediately after the defect mechanism causing the stuck-at chain failure. This work demonstrates a novel method for rapid scan chain fault isolation that significantly improves localization efficacy over conventional best-known methods (BKM) based on frequency mapping. Moreover, experimental results are presented to demonstrate that LIFA can be extended to interrogate the data state of flip flops in a scan chain. Results are also presented to establish that LIFA can be configured as a hardware-based diagnostics platform.

GHz scanning acoustic microscopy (GHz-SAM) was successfully applied for non-destructive evaluation of the integrity of back end of line (BEOL) stacks located underneath wire-bond pads. The current study investigated two sample types of different IC processes. Realistic bonding defects were artificially induced into samples and the sensitivity of the acoustic GHz-microscope towards defects in BEOL systems was studied. Due to the low penetration depth in the acoustic GHz regime, a specific sample preparation was conducted in order to provide access to the region of interest. However, the preparation stopped several microns above the interfaces of interest, thus avoiding preparation artifacts in the critical region. Cratering related cracks in the bond pads have been imaged clearly by GHz-SAM. The morphology of the visualized defects corresponded well with the results obtained by a chemical cratering test. Moreover, delamination defects at the interface between ball and pad metallization were detected and successfully identified. The current paper demonstrates non-destructive inspection for bond-pad cratering and ball-bond delamination using highly focused acoustic waves in the GHz-band and thus illustrates the analysis of micron-sized defects in BEOL layer structures that are related to wire bonding or test needle imprints.

Mechanical stress is a critical parameter in the design and manufacture of devices in very large scale integrated (VLSI) circuits. Whether intentionally introduced or parasitic, mechanical stress in nanoscale silicon technologies can alter carrier mobility as by as much as 25%, which can significantly affect device performance. Currently stress metrology for in-line production is conducted only at a wafer monitor level. For design purposes, the stress state in active device regions is usually inferred from electrical data. In this paper an instrument which we have developed is described for measuring mechanical stress in nanoscale silicon devices with high spatial resolution using scanning surface photovoltage microscopy (SSPVM). Other existing techniques are generally not suitable for making such measurements on production silicon nano-device structures in situ.

Through Silicon Via (TSV) is the most promising technology for vertical interconnection in novel three-dimensional chip architectures. Reliability and quality assessment necessary for process development and manufacturing require appropriate non-destructive testing techniques to detect cracks and delamination defects with sufficient penetration and imaging capabilities. The current paper presents the application of two acoustically based methods operating in the GHz-frequency band for the assessment of the integrity of TSV structures.

In this paper, we present a technique for device temperature measurement using spontaneous near infrared (NIR) emission from an Integrated Circuit (IC). By leveraging modeling and data analysis, time-integrated emission measurements are used to estimate the temperature increase due to switching activity inside the channel of CMOS transistors. The non-invasive nature of the technique allows one to reliably monitor the temperature of any device on-chip without the need for circuit modifications or dedicated on-chip sensors and with a higher spatial resolution than thermal cameras. This method has important applications for modeling heat dissipation during early process development, localizing hot spots, calibrating on-chip sensors, etc. In this paper, temperature is estimated by fitting empirical emission data to an emission model that can be solved for device channel temperature.

This paper provides a detailed analysis on the optical detection of temperature effects in FinFETs via (spectral) photon emission microscopy (SPEM/PEM) with InGaAs detector and electro-optical frequency mapping (EOFM, similar to LVI) for 14/16 nm Qualcomm Inc. FinFETs. It analyzes physical parameters of the FinFETs such as electron temperature and the relation between signal curve and operating condition of the device by photon emission slopes and spectra. The paper also traces device self-heating effects within the FinFETs by means of EOFM signal courses. With EOFM it was possible to detect self-heating effects of the FinFETs providing a further method to estimate device and substrate heating. Results showed that it is possible to obtain valuable device parameter information (for example, electron temperatures and self-heating) via optical investigations (PEM/ EOFM), which are not accessible electrically in modern integrated circuits. This information adds further details to device reliability and functionality approximations.

Magnetic current imaging (MCI) is an effective method for the isolation of individual integrated circuit (IC) current paths [1]. MCI is therefore useful in localizing open/short defects. In the case of a short, the failure current must be large enough to enable the detection of the magnetic field; however, in the case of the open failure, the current is very weak and detection can be limited by the wiring capacitance and modulation frequency. Often, magnetic sensor sensitivity is a function of the sensor size. Superconducting Quantum Interference Device (SQUID) sensors can detect weak current in an open failure, but the resolution is limited by the sensor size and can be difficult to utilize for IC applications. A Giant Magnetic Resistance (GMR) sensor has enough resolution [2], but cannot achieve enough sensitivity till now. This paper will present the use of Magneto-Optical Frequency Mapping (MOFM) using a 532nm light source. In addition, this paper will describe a specific IC application for an open failure measurement. For this technique, the MO crystal (sensor material) is placed directly on the DUT (a wiring test sample). This paper will demonstrate that the magnetic field modulation from AC current in open wirings can be detected. In addition, the details of the AC current path can be visualized using a Magneto-Optical based MCI measurement. Finally, the open point in the failing circuit will be shown to be isolated with an accuracy of a few tens of micrometers.

Visible light laser voltage probing (LVP) for backside improved optical spatial resolution is demonstrated on ultrathinned bulk Si samples. A prototype system for data acquisition, a method to produce ultra-thinned bulk samples as well as LVP signal, imaging, and waveform acquisition are described on bulk Si devices. Spatial resolution and signal comparison with conventional, infrared LVP analysis is discussed.

A modulated laser beam in the form of a continuous pulse train is explored on Laser Assisted Device Alteration (LADA). We term this pulsed-LADA to differentiate from conventional continuous wave (cw)-LADA. It is found that a duty cycle of less than 0.9 at low frequency above 1 kHz is sufficient to experience significant enhancements in laser stimulation. Following this, a new derivative of LADA technique called Electrically-enhanced LADA (EeLADA) is developed. Experimental results to demonstrate its capability in improving diagnostic resolution and potential application to hard failure debug will be presented.

A laser based logic state imaging (LLSI) by activating transient voltage collapse (TVC) circuits of SRAM blocks is demonstrated. In order to induce a voltage modulation on a power rail, significant numbers of TVC units are activated. The image quality of LLSI strongly depends on a number of activated TVC circuits. From this experiment, it is concluded that an additional circuit or experimental setup is not necessary for LLSI.

In this paper, we present a novel system and method for the automated mapping of pattern and spontaneous photon emission from very large areas of VLSI circuit using Solid Immersion Lens (SIL). To the best of our knowledge, this is the first time that such a technique has been developed and demonstrated on a real chip. The system being presented includes an automation software Application Programming Interface (API) to control the microscope used to acquire the images, an acquisition software that allows to automatically navigate the chip, move (hop) the SIL to the desired location, focus the image after the SIL landing, register the acquired images, and stitch them together to create a high resolution mosaic. In this paper, we will present, for the first time, a real life example involving thousands of images acquired from a 90 nm bulk technology test chip that were used to create a mosaic of more than 25 x 25 images covering a total area of approximately 400 x 400 μm2.

This work presents a new photon emission microscopy camera prototype for the acquisition of intrinsic light emitted from VLSI circuits during their normal operation. This novel camera was designed to be sensitive to longer wavelengths in order to maximize the signal intensities from modern VLSI chips which are characterized by a red shift in the intrinsic emission spectrum. In this paper, we will characterize the performance of the camera using 32 nm and 22 nm SOI chips. The novel camera is able to collect emission images with the circuit under test operating at a supply voltage down to 0.5 V, exceeding the performance of a state-of-the-art InGaAs camera.

Continuing advances in Atom Probe Tomography and Focused Ion Beam Scanning Electron Microscope technologies along with the development of new specimen preparation approaches have resulted in reliable methods for acquiring 3D subnanometer compositional data from device structures. The routine procedure is demonstrated here by the analysis of the silicon-germanium source-drain region of a field effect transistor from a de-packaged off-the-shelf 28 nm design rule graphics chip. The center of the silicon-germanium sourcedrain region was found to have approximately 180 ppm of boron and the silicide contact was found to contain both titanium and platinum.