With the 3D stack-die technology, top die and base die are stacked together with micro-bumps for die-to-die interconnection and a through silicon via (TSV) for die-to-package connection. This technology provides tremendous flexibility as designers seek to "mix and match" technology IP blocks with various memory and I/O elements in novel device form factors. Even though the lock-in thermal detection technique had been demonstrated as a useful debug technique to detect defects on packages or pin related fails on 3D stack-die configuration, it is difficult to apply this technique to do functional debug. This paper presents a novel base die debug technique with TSV wirebond for 3D stack-die devices. A comprehensive study on the base die debug flow with real failing cases is also presented. Base die debug techniques will need to continue to be innovated to provide complete debug solutions for such platform.

This paper presents novel optical beam-based defect localization approaches for resistive and open failed wafer-towafer (W2W) bonding interconnects for 3-D integration. The use of an etch back process in combination with thermal laser stimulation (TLS) and light-induced capacitance alteration (LICA) using visible laser excitation enables us to accurately pinpoint defects in high-density W2W interconnect structures down to a pitch of 2.2 µm. We confirm our results by focusedion beam (FIB) cross sectioning.

Correlation across applications and imaging platforms is essential and brings increased insurance for fault isolation in advance of destructive imaging. This paper demonstrates an approach for a detailed advanced packaging defect isolation and analysis workflow. To determine the effectiveness of the proposed workflow, a 28nm flip-chip was used as a test vehicle. By using this workflow, the yield in determining the fault location has increased from 60% to over 85%. To further improve the result, a surface charging mitigation scheme was used and the resulting measured correlative offset between the two systems was found to be less than 10um. This creates novel opportunities in reducing the size of the cross-section and increasing the overall throughput to find the defect, with high confidence. This workflow creates unique abilities in fault localization and analysis as it can detect both opens and shorts between the different techniques that are employed.

As the semiconductor industry demands higher throughput for failure analysis, there is a constant need to rapidly speed up the sample preparation workflows. Here we present extended capabilities of the standard Xe plasma Focused Ion Beam failure analysis workflows by implementing a standalone laser ablation tool. Time-to-sample advantages of such workflow is shown on four distinct applications: cross-sectioning of a large solder ball, cross-sectioning of a deeply buried wire bond, cross-sectioning of the device layer of an OLED display, and removing the MEMS silicon cap to access underlying structures. In all of these workflows we have shown significant decrease in required process time while altogether avoiding the disadvantages of corresponding mechanical and chemical methods.