Non-planar semiconductor devices, such as vertical fin-based field-effect transistor (FinFET) devices have been developed that include multiple vertical fins serving as conducting channel regions to enable larger effective conduction width in a small layout area. However, as circuits are scaled to smaller dimensions, it has become increasingly difficult to improve the performance of FinFET devices. Stacked nanosheet FETs have been developed to further enable larger effective conduction width in a given small layout area while enabling gate length scaling. Nanosheet (NS) FET devices have attracted attention as a candidate to replace FinFET technology at the 5 nm technology node and beyond due to their excellent electrostatics and short channel control. The use of silicon-germanium for the channel material has been explored as a major technology element for FinFET CMOS technology, and the performance benefits of Si-Ge channel over silicon channel have been demonstrated. Compared with conventional FinFET, stacked gate-all-around (GAA) NS CMOS shows higher electron mobility for nFET but lower hole mobility for pFET due to its unique device architecture and carrier transport direction. To improve pFET performance, SiGe NS is proposed as the pFET channel material. However, introducing and maintaining strain in the SiGe GAA NS channel is challenging but important for improving carrier transport. It is critical to understand the strain distribution in the advanced 3D nanosheet FET structures. This paper describes the use of advanced transmission electron microscopy (TEM) techniques to investigate the strain distribution in strained SiGe channel NS pFET through Si channel trimming and selective Si1-xGex epitaxial growth. A stacked GAA NS pFET was fabricated from compressively strained Si1-xGex channel with good crystallinity and high uniaxial compressive stress of ~1 GPa. From lattice deformation maps with a nanometer spatial resolution obtained by TEM techniques, the authors demonstrate that nano-beam precession electron diffraction techniques can be used to investigate the local strain distribution of the stacked GAA NS pFET devices with high precision, and thus help to optimize the integration process and strain engineering for pFET device performance enhancement for the next generation of CMOS logic in GAA NS technology.

Semiconductor devices are decreasing in dimensions and currently comprise stacks of ultrathin layers as in a spin-transfer torque magnetoresistive random-access memory (STTMRAM) device. For successful characterization by transmission electron microscopy (TEM) for failure analysis and device development, an accurate and controllable thinning of TEM specimens for is desirable. In this work, we combine plan view Ga focused ion beam (FIB) and post-FIB Ar milling preparation to prepare TEM specimens from a STT-MRAM device. Post-FIB Ar milling technique as a final polishing step of plan view TEM specimens was shown to prevent exposure of the tunnel barrier layer that can be damaged by the Ga FIB beam. We discuss the plan view FIB preparation, post-FIB Ar milling step and image analysis of the TEM images.

Moore’s law has been a major driving force in the development of novel semiconductor devices and has continued to hold its relevance over the years. The resultant, smaller and more powerful, microprocessors not only cater to the ever-increasing demands of the existing needs but also are important enablers of novel applications and discoveries in different areas. Several critical features of these latest devices are in the atomic to nanometer scale, which has enhanced the necessity of a largescale transmission electron microscopy (TEM) imaging-based metrology and failure analysis for their process development. As a result, the automation of lamella preparation using focused ion beam (FIB) and TEM imaging has gathered an enormous momentum in last few years. A key aspect of automating a large-scale TEM sample preparation not only involves the calibration of a given FIB tool to achieve an acceptable and repeatable quality of TEM samples but also to ensure that sample quality is consistent across the entire fleet of toolsets. In this work, the performance of three ThermoFisher Exsolve toolsets using a common tool calibration method for both, lamella thickness and targeting, has been compared. It was found that in general, thickness of TEM lamella showed a larger variation as compared to targeting over the period of one month. Lamella thickness showed a decreasing trend, and it entailed a need of recalibrating the tools in an interval of two weeks so that the variation in both thickness and targeting for the fleet can be kept within the desired specifications of ±3 nm (2σ).

This presentation shows how transmission electron microscopy (TEM) is used in semiconductor failure analysis to locate and identify defects based on their physical and elemental characteristics. It covers sample preparation methods for planar, cross-sectional, and elemental analysis, reviews the capabilities of different illumination and imaging modes, and shows how beam-specimen interactions are employed in energy dispersive (EDS) and electron energy loss spectroscopy (EELS). It describes the various ways transmission electron microscopes can be configured for elemental analysis and mapping and reviews the advantages of scanning TEM (STEM) approaches. It also provides an introduction to energy-filtered TEM (EFTEM) and how it compares with other TEM imaging techniques.

This paper describes optical and electron beam based fault isolation approaches for short and open defects in nanometer-scale through-silicon via (TSV) interconnects. Short defects are localized by photon emission microscopy (PEM) and optical beam-induced current (OBIC) techniques, and open defects are isolated by active voltage contrast imaging in a scanning electron microscope (SEM). The results are confirmed by transmission electron microscopy (TEM) cross-sectioning.

Transmission electron microscopy (TEM) is a widely used technique in semiconductor device failure analysis. A common challenge in TEM is electron radiation damage, which can generate an uncertainty for correct analysis. This paper reports a study of the electron beam-radiation damages in small technology nodes semiconductor devices relating to the FINFET sidewall and metal layer. The study is performed at three different high tensions at 200kV, 60kV, and 30kV to compare the electron beam-radiation damages. The paper demonstrates that using lower high tension is preferred for minimizing the electron beam-radiation damage in advanced semiconductor devices. However, it also shows that the lowest high tension might not always be suitable for certain semiconductor device regions.

Gate oxide breakdown has always been a critical reliability issue in Complementary Metal-Oxide-Silicon (CMOS) devices. Pinhole analysis is one of the commonly use failure analysis (FA) technique to analysis Gate oxide breakdown issue. However, in order to have a better understanding of the root cause and mechanism, a defect physically without any damaged or chemical attacked is required by the customer and process/module departments. In other words, it is crucial to have Transmission Electron Microscopy (TEM) analysis at the exact Gate oxide breakdown point. This is because TEM analysis provides details of physical evidence and insights to the root cause of the gate oxide failures. It is challenging to locate the site for TEM analysis in cases when poly gate layout is of a complex structure rather than a single line. In this paper, we developed and demonstrated the use of cross-sectional Scanning Electron Microscope (XSEM) passive voltage contrast (PVC) to isolate the defective leaky Polysilicon (PC) Gate and subsequently prepared TEM lamella in a perpendicular direction from the post-XSEM PVC sample. This technique provides an alternative approach to identify defective leaky polysilicon Gate for subsequent TEM analysis.

Multipurpose sample holder for advanced Transmission Electron Microscopy (TEM) sample preparation which reduces cost of the tool and most importantly simplifies the workflow is introduced. Following the current demand for user-friendly interface, semi-automated approach is aimed to be build up. Abilities to prepare advanced TEM lamellae in various geometries without rotary nanomanipulator and using various end-point detection signals are perceived as biggest advantages of this design.

Redistribution layer (RDL) bonding pad over active circuitry is utilized to re-route the original bond pad to other location for wire bonding using RDL. The damages in the active circuitry beneath the RDL bond pad induced by stress from wire bonding and package must be evaluated for reliability in the product development. The experimental approach and test structures are proposed in this paper. Functional fail was detected in electrical test after reliability tests on packaged IC. The dielectric cracking initiated by wire bonding that corresponds to the functional fail is identified by physical failure analysis and Transmission-Electron-Microscopy (TEM) at a specific location beneath the RDL bond pad. Finite element simulations are used to analyze the wire bonding stress distribution and circuit-under-pad design effect. The predicted maximum stress for the dielectric cracking matches to the location observed in the physical failure analysis. Based on the experiment and the simulation data, design rules for the circuit routing beneath the RDL bond pad have been successfully developed that all product reliability tests pass later with extend bonding power. The results lead to significant improvements in the robustness of circuit routing structure beneath the RDL bond pad for dielectric cracking without modifications of the existing processes for the product.

Reliability tests, such as Time-Dependent Dielectric Breakdown (TDDB), High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Those reliability tests are more stringent and complex especially for automotive Complementary Metal–Oxide–Semiconductor (CMOS) devices, this because it involves human lives and safety. In foundries failure analysis (FA), Transmission Electron Microscopy (TEM) analysis often required in order to provide insights into the defect mechanisms and the root cause of the reliability tests. In this paper, application of high resolution Nano-probing Electron Beam Absorbance Current (EBAC), Nano-probing active passive voltage contrast (APVC), and TEM with Energy Dispersive X-Ray Spectroscopy (EDX) to identify the failing root cause of Inter- Poly Oxide (IPO) TDDB failure on an automotive grade Non- Volatile Memory (NVM) device was investigated. We have successfully demonstrated that TEM analysis after Nanoprobing EBAC/APVC fault isolation is an effective technique to reveal the failure root cause of IPO breakdown after reliability stresses.

Demarest et al. concluded in their previous report that a ten times improvement in placement accuracy was required to enable automated transmission electron microscopy (TEM) sample preparation, and wafer alignment by GDS coordinates demonstrated a factor of two improvement in comparison to optical or scanning electron microscope based processes. This paper provides an additional update on this project. The study is about a GDS based process developed to simplify the complicated workflow for examining discrete electrical failures. The results of this study indicated that the recipe prototype developed on a test structure had a unique feature that consisted of an approximately 45nm by 200nm Cu line segment. Executing the prototype recipe on a wafer at the same process point fabricated 6 months after the original wafer yielded four identical successful samples of about 30nm sample thickness. This technique can thus be extended to large 2D arrays of small structures.

Dopants imaging using scanning capacitance microscopy (SCM) and scanning spreading resistance microscopy are used for identifying doped areas within a device, the latter being analyzed either in a top view or in a side view. This paper presents a sample preparation workflow based on focused ion beam (FIB) use. A discussion is then conducted to assess advantages of the method and factors to monitor vigilantly. Dealing with FIB machining, any sample preparation geometry can be achieved, as it is for transmission electron microscopy (TEM) sample preparation: cross-section, planar, or inverted TEM preparation. This may pave the way to novel SCM imaging opportunities. As FIB milling generates a parasitic gallium implanted layer, a mechanical polishing step is needed to clean the specimen prior to SCM imaging. Efforts can be conducted to reduce the thickness of this layer, by reducing the acceleration voltage of the incident gallium ions, to ease sample cleaning.

Transmission electron microscopy (TEM) sample can be routinely made at a sub 30nm thickness and specific features in semiconductor device design are on the order of 30nm and smaller. As a result, small changes in pattern match registration can significantly influence the success or failure of proper TEM sample placement as an approximately 15nm shift in lamella placement can easily cause the sample to be off the feature of interest. To address this issue, design based recipe writing is being developed on a dual beam focused ion beam platform. The intent is to have the tool read a GDS file and pattern match the design information to physical wafer images in a similar fashion to state-of-the-art critical dimension scanning electron microscopy operation. While the results are very encouraging, more work needs to be done to ensure a TEM sample of approximately 30nm thickness is placed at the desired location.

Transmission electron microscopy (TEM) specimens are typically prepared using the focused ion beam (FIB) due to its site specificity, and fast and accurate thinning capabilities. However, TEM and high-resolution TEM (HRTEM) analysis may be limited due to the resulting FIB-induced artifacts. This work identifies FIB artifacts and presents the use of argon ion milling for the removal of FIB-induced damage for reproducible TEM specimen preparation of current and future fin field effect transistor (FinFET) technologies. Subsequently, high-quality and electron-transparent TEM specimens of less than 20 nm are obtained.

The State-of-the-Art FinFET technology has been widely adopted in the industry, typically at 14 nm and below technology nodes. As fin dimensions are pushed into the nanometer scale, process complexity is highly escalated, posing great challenges for physical failure analysis. Meanwhile, the accelerated cycles of learning for new technology nodes demand high accuracy and fast turnaround time to solve the material and interface issues pertaining to semiconductor processing or device failure. In this paper, we report a case study of fin related defect that caused device failure. Several analytical techniques, namely, Scanning Electron Microscopy (SEM), plan-view and cross-section Transmission Electron Microscopy (TEM) with Energy Dispersive X-ray spectroscopy (EDX), Electron Energy Loss Spectroscopy (EELS) and Z-contrast tomography were employed to characterize the defect and identify root-cause, leading to the resolution of this issue.

In transmission electron microscopy (TEM), one typically considers bright-field or dark-field imaging signals, which utilize the transmitted and scattered electrons, respectively. Analytical signals such as characteristic X-Rays or primary electron beam energy losses from inelastic scattering events give rise to the energy dispersive X-Ray spectroscopy and electron energy loss spectroscopy techniques, respectively. In this paper, the detection of the electron beam absorbed current (EBAC) and electron beam induced current (EBIC) signals is reported using a specially designed scanning TEM holder and associated amplification electronics. By utilizing thin TEM samples where the beam-sample interaction volume is controlled more through the incident electron probe size, the EBAC and EBIC signal resolution is improved to the point where implant regions and Schottky junction depletion zones can be visualized.

Forming and breaking a nanometer-sized conductive area are commonly accepted as the physical phenomenon involved in the switching mechanism of oxide resistive random access memories (OxRRAM). This study investigates a state-of-the-art OxRRAM device by in-situ transmission electron microscopy (TEM). Combining high spatial resolution obtained with a very small probe scanned over the area of interest of the sample and chemical analyses with electron energy loss spectroscopy, the local chemical state of the device can be compared before and after applying an electrical bias. This in-situ approach allows simultaneous TEM observation and memory cell operation. After the in-situ forming, a filamentary migration of titanium within the dielectric hafnium dioxide layer has been evidenced. This migration may be at the origin of the conductive path responsible for the low and high resistive states of the memory.

The sub-nanometer resolution that transmission electron microscopy (TEM) provides is critical to the development and fabrication of advanced integrated circuits. TEM specimens are usually prepared using the focused ion beam, which can cause gallium-induced artifacts and amorphization. This work presents the use of a concentrated argon ion beam for reproducible TEM specimen preparation using automatic milling termination and targeted ion milling of device features; the result is high-quality and electron-transparent specimens of less than 30 nm. Such work is relevant for semiconductor product development and failure analysis.

This paper provides an innovative root cause failure analysis method that combines multiple failure analysis (FA) techniques to narrow down and expose the shorting location and allow the material analysis of the shorting defect. It begins with a basic electrical testing to narrow down shorting metal layers, then utilizing mechanical lapping to expose over coat layers. This is followed by optical beam induced resistance change imaging to further narrow down the shorting location. Scanning electron microscopy and optical imaging are used together with focused ion beam milling to slice and view through the potential shorting area until the shorting defect is exposed. Finally, transmission electron microscopy (TEM) sample is prepared, and TEM analysis is carried out to pin point the root cause of the shorting. This method has been demonstrated successfully on Western Digital inter-metal layers shorting FA.

When failure analysis is performed on a circuit composed of FinFETs, the degree of defect isolation, in some cases, requires isolation to the fin level inside the problematic FinFET for complete understanding of root cause. This work shows successful application of electron beam alteration of current flow combined with nanoprobing for precise isolation of a defect down to fin level. To understand the mechanism of the leakage, transmission electron microscopy (TEM) slice was made along the leaky drain contact (perpendicular to fin direction) by focused ion beam thinning and lift-out. TEM image shows contact and fin. Stacking fault was found in the body of the silicon fin highlighted by the technique described in this paper.