This paper discusses the development of an electrical failure analysis workflow that uses a multifunction direct current tester (DCT) to map the location of defects associated with open and short circuits as well as leakage current. It explains how software and tooling were designed to accommodate a wide range of package types and sizes and how they were verified by testing. It also presents two case studies showing the accuracy of the defect mapping function for sockets with 0.8 and 1.0 mm ball pitch.

This paper uses an interesting specific case study to highlight the non-destructive fault isolation demonstration of 3DIC stacked dies applied the optical beam induced resistance change (OBIRCH) approach.

An advanced method for LF (Lead Free) bump sample preparation to improve the surface of sample that can enhance the image of IMC (Inter Metallic Compound), solder grain boundary and micro-crack after TC (thermal cycle) reliability test is proposed. By this advanced method application, LF bump micro-crack location and propagation path can be observed easily for the reliability test fracture failure mechanism study and LF bump crack improvement further.

The emission microscopy effectiveness has been proven in detecting a variety of IC process leakage defects over the years. However this technique shows limitation on high resistance backend process defects localization, especially on function failures with frequency dependent but without leakage current. This paper introduces three trigger algorithms to enable precisely and directly defects localization of high resistance interconnects.