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Xijiang Lin
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Proceedings Papers
ISTFA2008, ISTFA 2008: Conference Proceedings from the 34th International Symposium for Testing and Failure Analysis, 383-389, November 2–6, 2008,
Abstract
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Abstract In this paper, we describe a silicon debug flow that uses debug-friendly scan test patterns to improve the efficiency of physical fault isolation of timing failures using time-resolved emission (TRE) system. Several techniques have been developed to generate the debug-friendly test patterns. We further show a silicon debug case of a 90nm design based on the proposed debug flow.
