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Tsu Hau Ng
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Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 511-516, November 3–7, 2013,
Abstract
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Abstract Conductive-Atomic Force Microscopy (C-AFM) is a popular failure analysis method used for localization of failures in Static Random Access Memory (SRAM) devices [1-4]. The SRAM structure has a highly repetitive pattern where any abnormality in a failed cell compared to neighboring cells could be easily identified from its current image [5-7]. Unlike topographical imaging, the C-AFM requires the probe tip to be coated with a conductive layer in order to pick up the electrical signals from the device under test. The coating needs to be sufficiently thick as it would wear off after a certain amount of physical scanning. This additional coating on the AFM tip is essential but poses a limit to the tip radius curvature. The commercially available tip radius is approximately 35nm (DDESP-10 from Bruker) and the dimension is too large for imaging of 20nm technology device. However, the limitation could be alleviated by subjecting the sample surface to treatment prior to C-AFM imaging. The aim of this surface treatment is to ensure C-AFM tip maintains sufficient scanning contact with the tiny conductive (tungsten) structure of the sample in order to achieve distinct current image. The surface treatment is done by creating a receding Inter-Layer Dielectric (ILD) from its neighboring tungsten contact. The creation of the receding depth could be achieved by either wet etching or dry etching (Reactive Ion Etching, RIE). In this work, the surface treatments by these two methods have been investigated and the recipe is optimized to obtain a clear current image. The optimized recipe is then applied on actual failure analysis where three cases are studied.
Proceedings Papers
ISTFA2013, ISTFA 2013: Conference Proceedings from the 39th International Symposium for Testing and Failure Analysis, 517-522, November 3–7, 2013,
Abstract
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Abstract With the shrinkage of the IC device dimensions, Cu and ultra-low-k dielectric were introduced into IC devices to reduce RC delay. Ultra-low-k dielectrics generally suffer more damage than silicon oxide dielectric during process integration and subsequently cause reliability degradation. Therefore, ultra-low-k damage characterization on Cu damascene structures is of great importance to understand the damage mechanisms. This paper describes the application of UV-Raman microscopy with enhanced spatial resolution and signal sensitivity for characterizing ultra-low-k dielectric in the three-dimension structure of Cu metallization with nanometer feature size. It shows UV-Raman technique has an advantage in analyzing ultra-low-k layer on patterned wafer and extracting ultra-low-k signals from Cu/ultra-low-k mixed structure. UV-Raman is also effective to characterize the ultra-low-k degradation for ultra-low-k related reliability analysis by time dependent dielectric breakdown (TDDB) test.