Abstract Building a portfolio of deformations is the key step for building better defect models for the test and yield learning domain. A viable approach to achieve this goal is through geometric characterization and classification of failure patterns found on memory fail bitmaps. In this paper, we present preliminary results on how to build such a portfolio of deformations for an IC technology of interest based on a fail bitmap analysis study conducted on large, modern SRAM memory products.

Abstract This paper proposes a taxonomy of process-induced deformations of IC structures. Such a taxonomy is envisioned as a foundation for yield modeling and development of test strategies, as well as, for design of ICs with redundancy. It is proposed to address the rapidly growing complexity of interaction between process-induced deformations of IC structures and steadily shrinking geometry of deep submicron ICs.

Abstract SRAM bit fail maps (BFM) are routinely collected during earlier phases of yield ramping, providing a rich source of information for IC failure and deformation learning. In this paper, we present an automated approach to analyzing BFM data efficiently. We also demonstrate the usability of our analysis framework using real BFM test data from a large, modern SRAM test vehicle.

Abstract We present a generalized method to attack fault diagnosis at the logic level that aims at localizing and differentiating fault types. In particular, we present an application of this method that aids in distinguishing opens and two-line shorts. While past work has addressed distinction between shorts and opens, we present an algorithm to generate more test patterns to narrow down the diagnosis callout based on type or location. In general, we are not limited to a few fault models as our description of the logic misbehavior is built on fault tuples. This becomes important in the area of fault and defect characterization. Results based on logic validation and SPICE simulations of extracted netlists indicate the usefulness and efficiency of our approach.