Abstract Transmission electron microscopy (TEM) [1] and scanning capacitance microscopy (SCM) [2] have become common failure analysis tools at Sandia for new product development, process validation, and yield enhancement. These two techniques provide information that cannot be obtained with other analytical techniques. The information provided by these two techniques has been instrumental in identifying the root causes of several yield-limiting defects in CMOS IC technologies at Sandia. This paper describes an example of how TEM and SCM have been used to identify the root causes of SOI device failures. The corrective actions taken to reduce defects and improve yield are also described.