This presentation provides an overview of chip-scale packages (CSPs) and the challenges they create for failure analysis. It begins with a review of stacked, multichip, and wafer-level packages, using images and illustrations to highlight complexities. It then presents examples of package-level failure mechanisms including various forms of cracking, inadvertent wire bond contact, and die-edge chipping. It likewise assesses die-level analysis challenges and provides practical solutions. The presentation also includes several case studies and describes new and emerging challenges.

This presentation provides an overview of chip-scale packages (CSPs) and the challenges they create for failure analysis. It begins with a review of stacked, multichip, and wafer-level packages, using images and illustrations to highlight complexities. It then presents examples of package-level failure mechanisms including various forms of cracking, inadvertent wire bond contact, and die-edge chipping. It likewise assesses die-level analysis challenges and provides practical solutions. The presentation also includes several case studies and describes new and emerging challenges.

The task of circuit repairing and debugging using a Focused-Ion-Beam system on multi-layered IC devices is often difficult and tedious, especially when desired or target metal nodes or layers are buried under other higher level or nontarget metal nodes or layers. As a result, not only are target nodes difficult to access, but also, undesired shorts are difficult to prevent. To further complicate the situation, as the number of metal layers increases, the lower level metal nodes become increasingly thinner, and the node population becomes increasingly denser. These conditions result in a decreased success rate utilizing the FIB and an increased turn-around time for design debugging. Besides significant improvement of the FIB equipment and tools, new techniques that can be used to overcome the difficulties encountered during FIB operations on multi-layered IC devices need to be utilized. In this paper, we will focus on discussion of some new techniques that can be used for FIB device modification work and device debugging on multi-layered IC devices, including C4 (controlled-collapse chip connection) flip-chip devices. Some recommendations and tips for using these techniques on complicated fib modification work will also be shared based on the author’s experience.