Abstract A variety of EFA techniques have been deployed to improve scan chain failure isolation. In contrast to other laser techniques, modulation mapping (MM) does not require electrically perturbing of the device. Beginning with a review of MM and continuous-wave (CW) probing as well as shift debug using MM, this paper presents three case studies involving scan chains with subtle resistive and leakage failure mechanisms, including transition, bridge, and slow-to-rise/fall failures, using a combination of these techniques. Combining modulation mapping with laser probing has proven to be a very effective and efficient methodology for isolating shift defects, even challenging timing-related shift defects. So far, every device submitted for physical failure analysis using this workflow has led to successful root cause identification. The techniques are sufficiently non-invasive and straightforward that they can be successfully applied at wafer level for volume, yield-oriented EFA.

Abstract Laser Voltage Imaging (LVI) is a new application developed from Laser Voltage Probing (LVP). Most LVP applications have focused on design debug or design characterization, and are seldom used for global functional failure analysis. LVI enables the failure analysis engineer to utilize laser probing techniques in the failure analysis realm. In this paper, we present LVI as an emerging FA technique. We will discuss setting up an LVI acquisition and present its current challenges. Finally, we will present an LVI application in the form of a case study.

Abstract Yield on specific designs often falls far short of predicted yield, especially at new technology nodes. Product-specific yield ramp is particularly challenging because the defects are, by definition, specific to the design, and often require some degree of design knowledge to isolate the failure. Despite the wide variety of advanced electrical failure analysis (EFA) techniques available today, they are not routinely applied during yield ramp. EFA techniques typically require a significant amount of test pattern customization, fixturing modification, or design knowledge. Unless the problem is critical, there is usually not time to apply advanced EFA techniques during yield ramp, despite the potential of EFA to provide valuable defect insight. We present a volume-oriented workflow integrating a limited set of electrical failure analysis (EFA) techniques. We believe this workflow will provide significant benefit by improving defect localization and identification beyond what is available using test-based techniques.

Abstract In this paper we evaluate the possibility of extending Time Resolved Emission (TRE) technology towards future low voltage SOI technologies. In particular, we investigate and quantify the gain offered by the InGaAs detector improvements devised by Credence Corp., now DCG Systems, the manufacturer of the Emiscope III PICA system used in this analysis. Experiments on a test chip fabricated in the IBM SOI 65 nm technology will demonstrate that the improved tool guarantees the same Signal-to-Noise Ratio (SNR) even at ~90 mV lower supply voltages. In the second part of the paper we also discuss various other acquisition optimizations of the system. Although the analysis presented here refers to a specific tool, the large majority of the results and discussions can easily be generalized and applied to other PICA systems and detectors, as well as low voltage bulk silicon technologies.

Abstract In this paper, we demonstrate two applications of time-resolved emission (TRE): measurement of dynamic, local power-supply (Vdd) variations, and synchronous timing jitter induced by Vdd variations. The first technique measures the height of many peaks within a TRE waveform; differences in peak height are correlated with inter- pulse differences in Vdd. The second technique measures the timing of all of the peaks and extracts the inter-pulse timing variations. The measurement was automated and was performed on long (multiple-μs) acquisition windows containing hundreds of emission peaks. Our work advances the state of the art by using the peak heights and positions to extract this information, and by performing the measurements in an automated fashion.

Abstract Internal node timing probing of silicon integrated circuits (ICs) has been a mainstay of the microelectronics industry since very early in its history. In recent years, however, due in part to the increase in the number of interconnection layers and continued proliferation of packaging techniques exposing only the silicon substrate, conventional probing technologies such as e-beam and mechanical probing have become cumbersome or impractical. In an effort to continue transistor-level probing, backside optical probing technologies have been developed and adopted [1]. Chronologically, such techniques include picosecond image circuit analysis (PICA)[2], laser voltage probing (LVP)[3], and dynamic or time-resolved emission (TRE)[4]. In typical examples of backside probing the device under test (DUT) relies on device stimulation from automatic test equipment (ATE) or equivalent bench top setup. This generally requires a specially designed DUT card designed to accommodate a low-profile socket and lid. The DUT card, which is significantly smaller than the tester motherboard, is designed to fit within the chamber opening of the probe system in order to interact with the optical column. Tester stimulation of packaged parts, however, does not address the need to probe the DUT in-situ and in the intended application, such as a PC board. It is often desirable to probe the DUT under conditions typical of the final product or running standardized application based tests. We present here this application and have addressed some of the challenges associated with PC card based optical probing and show successfully performed time-resolved emission on a second-generation advanced graphics processor in a standard graphics card.

Abstract Dynamic hot-electron emission using time-resolved photon counting can address the long-term failure analysis and debug requirements of the semiconductor industry's advanced devices. This article identifies the detector performance parameters and components that are required to scale and keep pace with the industry's requirements. It addresses the scalability of dynamic emission with the semiconductor advanced device roadmap. It is important to understand the limitations to determining that a switching event has occurred. The article explains the criteria for event detection, which is suitable for tracking signal propagation and looking for logic or other faults in which timing is not critical. It discusses conditions for event timing, whose goal is to determine accurately when a switching event has occurred, usually for speed path analysis. One of the uses of a dynamic emission system is to identify faults by studying the emission as a general function of time.

Abstract Two optical techniques are currently available for making at-speed timing measurements through the backside of CMOS integrated circuits: Laser Voltage Probing and Picosecond Imaging Circuit Analysis. These techniques differ significantly in many ways, including potential for invasiveness, Silicon-On- Insulator probing capability, acquisition times versus test pattern loop length, data acquisition mode, and prospects for probing at the 0.1 μm nodes. This paper compares and contrasts these techniques so that their relative merits and limitations can be better understood.

Abstract A new tool (Schlumberger IDS 2000) has become available for acquiring waveforms from C4 (also known as flip chip) packaged IC’s. The waveform acquisition technique is based on electro-optic sampling through the backside of silicon. After explaining the physics of electro-optic sampling, the technique is demonstrated through the backside of Si on a simple diode test structure and a flip chip microprocessor. Also, many of the issues and challenges with this tool are discussed.