Abstract Backside photoemission microscopy [1-2] was used to analyze the major yield loss of a communication product fabricated with submicron CMOS process: functional failures of phase-lock-loop (PLL). The PLL block was covered by five metal layers and three of them were bulk metals. Based upon the backside photoemissions detected on the capacitor structures within the PLL block and the ruptures observed at the emission spots on the polysilicon and gate oxide or of the capacitor after physical deprocessing, the failure was proved due to the capacitor gate-oxide breakdown. This was believed to be caused by the plasma-induced-damage during high-density-plasma (HDP) CVD oxide deposition after the front-end processes, as only the lots from one HDP-CVD deposition equipment have very high percentage PLL functional failure. Subsequent machine commonality check did find non-uniform inter layer dielectric (ILD) thickness from this equipment, which indicated the non-uniform plasma intensity occurred during the ILD film deposition. This was further confirmed by the finding of a worn-out gas-shower-head in this system. The abnormal high density of plasma created extra charging and caused the PLL poly capacitor’s gate oxide breakdown due to the antenna effect. After replacing the gas showerhead, the failure disappeared and yield was back to normal. Through this low yield analysis, we demonstrated an effective application of backside photoemission microscopy to fab yield improvement.

Abstract As integrated circuits’ geometry are reduced by about 0.7 for each new generation, failure analysis becomes more challenging in fault isolation and physical deprocessing to determine the root cause of the failure. It is impossible to deprocess the device by conventional wet-etch method as metallization tends to be etched or lifted off using all known wet chemicals. Currently the deprocessing techniques can be classified into two categories: dry-etch plus mechanical polishing and full dry-etched methods. In Chartered a new deprocessing technique by combining selective wet-etching of passivation and Inter Metal Dielectric (IMD) layers and mechanical lapping/polishing have been developed. Selective removal of passivation and IMD layers is of major importance in failure analysis of semiconductor devices. The key objective of this technique is to etch away passivation and IMD layers without attacking any metallization. This new deprocessing technique enables failure analyst to delayer by wet-etch again even those submicron devices. It avoided dry etch related problem such as selectivity, temperature control, etch rate stability, RIE grass, side wall polymer and end point detection…etc. It offers a cheaper alternative method for deprocessing when the plasma etcher is not available.

Abstract In this paper, some low yield cases in Flat ROM device (0.45 and 0.6 µm) were investigated. To find killer defects and particle contamination, KLA, bitmap and emission microscopy techniques were used in fault isolation. Reactive ion etching (RIE) and chemical delayering, 155 Wright Etch, BN+ Etch and scanning electron microscope (SEM) were used for identification and inspection of defects. In addition, energy-dispersive X-ray microanalysis (EDX) was used to determine the composition of the particle or contamination. During failure analysis, seven kinds of killer defects and three killer particles were found in Flat ROM devices. The possible root causes, mechanisms and elimination solutions of these killer defects/particles were also discussed.

Abstract With further miniaturization of MOS devices, the thickness of gate oxides becomes thinner and thus more sensitive to damage. Emission microscopy has shown its capability in analysis of these failures. However, emission site is not always the exact location of the physical defect. High-density devices with multi-metal layers make the situation worse. But when it is combined with Passive Voltage Contrast (PVC) technique, the success rate of isolating such failures can be greatly increased. In a case study, a unit of 1M bits Static Random Access Memory (SRAM), fabricated by 0.25 µm technology with 5 metal layers, failed after 500 hours burn-in. We successfully isolated the leaky poly and subsequently found gate oxide pinholes with the combination of PVC technique and emission analysis.

Abstract In our previous paper [1], discolored bondpads due to galvanic corrosion were studied. The results showed that the galvanic corrosion occurred in 0.8 ìm wafer fabrication (fab) process with cold Al alloy (Al-Si, 0.8 wt%-Cu, 0.5 wt%) metallization. Galvanic corrosion is also known as a two-metal corrosion and it could be due to either wafer fab process or assembly process. Our initial suspicion was that it was due to a DI water problem during wafer sawing at assembly process. After that, we did further failure analysis and investigation work on galvanic corrosion of bondpads and further found that galvanic corrosion might be due to longer rinsing time of DI water during wafer sawing. The rinsing time of DI water is related to the cutting time of wafer sawing. Therefore, some experiments of wafer sawing process were done by using different sizes of wafer (1/8 of wafer, a quadrant of wafer and whole of wafer) and different sawing speed (feed-rate). The results showed that if the cutting time was longer than 25 minutes, galvanic corrosion occurred on bondpads. However, if the cutting time was shorter than 25 minutes, galvanic corrosion was eliminated. Based on the experimental results, it is concluded that in order to prevent galvanic corrosion of bondpads, it is necessary to select higher feed-rate during wafer sawing process at assembly houses. In this paper, we will report the details of failure analysis and simulation experimental results, including the solution to eliminate galvanic corrosion of bondpads during wafer sawing at assembly houses.