Abstract This paper describes techniques to prepare integrated circuit (IC) samples, containing a Thick Organic Dielectric (TOD) over Cu inductors, for Scanning Electron Microscopy (SEM) or Focused Ion Beam (FIB) editing. Our technique utilizes mechanical polishing and UV laser ablation in lieu of chemical decapsulation and deprocessing.

Abstract First silicon of a cost effective, BICMOS mixed signal RF/IF integrated circuit (IC) for third generation (3G) cellular phones showed high leakage current on the analog receive supply pins in “battery save” mode. Our tasks were to identify and isolate the source of leakage and to fix the design. Alternate debug techniques were used to isolate the cause of the leakage and provide a solution after inconclusive results were obtained using photon emission microscopy,(1) and infrared microthermography techniques.

Abstract A cost-effective, BICMOS mixed signal, RF/IF integrated circuit for cellular phones had high leakage current in “battery save” conditions. It was also susceptible to Electrostatic Discharge (ESD). Our tasks were to identify the source of leakage, to identify the reason for the low Electrostatic Discharge protection, and to fix the design. Design edits of the circuits were accomplished using Focused Ion Beam tool. This approach helped in verifying the design fix on the silicon before committing to expensive masks. The capabilities of Focused Ion Beam systems are rapidly becoming critical for Failure Analysis and design edits of submicron technology devices.

Abstract Infrared Micro Thermography can be applied as electrical fault identification in situations where photon emission is ineffective. Defects, such as certain types of stringers and particles, may conduct without emitting photons in the visible range. Arrayed infrared sensors such as an InSb 512x512 detector, coupled with the appropriate infrared optics can image the heat generated from the leakage site. Heating on the order of a fraction of a degree Kelvin can be observed. The heat signature can be superimposed on a normal optical image of the chip. Several practical examples using this fault identification technique are described.