Abstract Random single bit failures were encountered in cache areas of Motorola’s 0.13 µm CMOS products under development. Extensive in-line probe data and end-of-line probe data in conjunction with failure analysis indicated the presence of particles at the upper surface of tungsten contacts. This paper describes how TEM based techniques were used to analyze the origin of the defect which in turn enabled process optimization and yield improvement.

Abstract For its latest generation of high performance logic applications, Motorola employs a 0.13 µm CMOS technology with shallow trench isolation (STI). The contact dimension and spacing requirements for the dense areas of the circuitry, such as the cache, are quite aggressive. We recently encountered single bit and massive array failures, which were traced to an electrical short between tungsten contacts. We report here the failure analysis, which involved electrical and physical testing techniques.