Abstract The presence of crystalline defects, including dislocations and pipeline defect, is detrimental to both the processing and the intrinsic quality of semiconductor devices. The electrical parametric or functional failures generated by those defects require accurate identification and proper classification in a continuous improvement mindset. Depending on the failure analyst choice of the investigation technique, the distinction between a dislocation and a pipeline defect can be difficult. In this paper, based on case studies of mixed-mode devices, the various electrical and physical FA investigation techniques are explored and compared. From an electrical investigation standpoint, fault localization techniques will be reviewed (Thermal Laser Stimulation and Photon Emission Microscopy) as well as the direct electrical measurements means (external measurement and nanoprobing AFP). From a physical analysis standpoint, the use of various methods after deprocessing will be considered: top down delineation etch, Atomic Force Microscopy (AFM), Scanning Microwave Microscopy (SMM), and Transmission Electron Microscopy (TEM). The position of the defect as well as its physical signature observed through the various methods will determine its proper classification and will determine the appropriate corrective actions. The paper will be concluded with a discussion on the physical differences between a dislocation and a pipeline defect, as well as insights into the wafer fab manufacturing process.

Abstract Ultra-thin (<100 nm) flakes shorting metal lines are difficult to detect and often cause the device to fail after reliability stress or at the customer site. In most cases, the common technique of inspecting the device in an optical microscope followed by conventional low energy (<3.0 kV) scanning electron microscopy (SEM) is often not able to detect this type of defect. In rare cases, where the defect is successfully exposed by the traditional procedure, it is very challenging to perform additional transmission electron microscopy (TEM) characterization of the defect without introducing arifacts during sample preparation of the exposed flake. A new procedure to identify these defects using a combination of face-lapping and high energy (>10 kV) SEM imaging is described in this paper. In this method, the failing device is carefully face-lapped and inspected frequently using a high energy (>10 kV) scanning electron beam. The high energy electron beam penetrates through the oxide layer and detects features embedded below the oxide. This technique greatly incresases the chances of detecting the flake, as the method is capable of detecting the defect at a larger range of oxide thickness as opposed to the traditional method. Additionally, TEM results were improved when the ultra-thin flakes were detected below the surface with the high energy SEM technique. Several examples of ultra-thin flakes found using the high energy SEM vs. low energy SEM will be presented.

Abstract A selected area planar TEM (SAPTEM) sample preparation technique for failure analysis of integrated circuits using a transmission electron microscope has been developed. The technique employs a combination of mechanical grinding, selective wet/dry chemical etching (if required) and a two step focused ion beam IIFIB) milling. The mechanical grinding steps include: (a) a backside grind to achieve a die thickness less than 30 µm, (b) the support half ring glue, and (c) a cross-section grind from one side to reach less than 35 pm to the failing site. A selective wet or dry chemical etch is applied before, between,, or after FIB thinning depending on the nature of problem and device components. The FIB milling steps involve: (is) a high ion current cross-sectional cut to reach as close as 5-8 µm to the area of interest (b) a final planar thinning with the ion beam parallel to the surface of the die. The plan view procedure offers unique geometric advantage over the cross-section method for failure analysis of problems that are limited to silicon or certain layers of the device. Iln the cross-sectional approach, a thin section (thickness less than 250 µm) of a device is available for failure analysis, whereas in the planar procedure a 20 µm2 area of any layer (thickness less than 250 µm) of the device is available. The above advantage has been successfully exploited to identify and solve the following prablems in fast static random access memories (FSRAM): (i) random gateoxide rupture that resulted in single bit failures, (ii) random dislocations from the buried contact trenching that caused single bit failures and general silicon defectivity (e.g. implant damage and spacer edge defects), and (iii) interracial reactions.

Abstract Temperature sensitive single bit failures at wafer level testing on 0.4µm Fast Static Random Access Memory (FSRAM) devices are analyzed. Top down deprocessing and planar Transmission Electron Microscopy (TEM) analyses show a unique dislocation in the substrate to be the cause of these failures. The dislocation always occurs at the exact same location within the bitcell layout with respect to the single bit failing data state. The dislocation is believed to be associated with buried contact processing used in this type of bitcell layout.