Abstract This article analyzes the cause of Vcc shorts in advanced microprocessors. In one instance, an advanced microprocessor exhibited Vcc shorts at wafer sort in a unique pattern. The poly silicon was narrow in one section of the die. The gates were shown to measure small, but no electrical proof of the short could be seen. To prove the short existed as a result of the narrow gate, a Scanning Capacitance Microscope (SCM) was utilized to confirm electrical models, which indicated a narrow poly silicon gate would result in Vcc shorts. High frequency dry etching and UV-ozone oxidation were employed for deprocessing. The use of the SCM confirmed the proof that the Vcc shorts were caused by narrow gate length which causes its leaky behavior. This conclusion could have only been confirmed by processing of material through the wafer foundry at the cost of money and time.

Abstract Flip Chip packaging requires an understanding of the solder bump metallurgy and its aging characteristics. In this paper we demonstrate how standard failure analysis techniques can help determine aging characteristics and, how an understanding of bump age can be successfully employed to enhance bump reliability.