Abstract Passive voltage contrast (PVC) is a phenomenon seen while inspecting a semiconductor device where imaged circuit features have a different value of contrast depending on whether that feature has an electrical path to ground, another circuit element, or has an open connection. A common method of fault isolation during failure analysis is to use these contrast values to determine if a feature is incorrectly connected indicating a defect is present. This paper discusses a fault identification method by creating a simulated PVC reference that can be displayed next to the scanning electron microscope PVC image for a comparison of the expected PVC. The procedure of how to create the PVC reference is discussed using functions found in tools typically used to run a Design Rules Check in commonly available software. Three examples are given of how this methodology could be used to provide further analysis capabilities during fault isolation.

Abstract The formation of silicon defects in 0.18um and smaller technology nodes has become a challenging device level defect to identify and eliminate. In this paper, we present a new method of passive voltage contrast that was initially used to locate silicon defects, experimental results revealing the key contributors to the formation of these defects, and a method of in-line identification by correlating SEM based in-line defect inspections to end of line SRAM fail bit maps. Silicon defects that form along the edge of an active region connect the source and drain with a low resistance leakage path that are successfully detected at later processing layers using voltage contrast techniques with a SEM based In-line inspection tool as well as after processing by using our method of passive voltage contrast. The systematic nature of this defect produces a consistent SRAM memory fail mode of single column fails. When these silicon defects are present, single column fails dominate the usual single and double bit fail modes. The physical location of the failing columns can be mapped back to the defect locations produced from the in-line inspections. This method was utilized to interpret experimental results in an effort to determine process parameters that produce silicon defects. It was found that STI depth plays a key role in the formation of these defects. Experiments were run where the depth was intentionally put at worst case so that the effectiveness of several alternative processes to repair the defects could be evaluated. It was shown that modulating the STI liner oxidation temperature had the largest effect compared to several other process parameters.