Nanoprobing and subsequent electron beam induced current imaging technique are commonly used techniques for fault localization. The failing structure/device being electrically tested, the behavior of the electrical characteristics allows to give hypothesis of the origin of the fail, while single device testing enables to restrict the physical characterization to the failing structure - either using FIB/SEM cross-sectioning or for advanced technology nodes, directly with a TEM lamellae performed at pointed site location. In this paper, an experimental setup to perform electrical-like mappings on a TEM lamella is implemented, as an additional step to the existing nanoprobing-TEM flow. Such an apparatus offers the ability to observe indirectly dopants distribution in a TEM thin foil, allowing a direct complement from a TEM specimen. Moreover, when applied on thicker TEM-like samples, the technique ability to localize subtle defects prior their physical characterization is demonstrated.

In semiconductor industries, development of new technologies and new products generally follows a phase of yield improvement where Failure Analysis expertise is used to locate and fix killer defects and for design debug. When process and design reach a certain level of maturity, a second phase of optimization, qualification and reliability is executed in which Failure Analysis expertise is used for internal timing characterization of integrated circuit and results are compared with design/process simulations. In order to reduce the cost of testing during manufacturing, circuits embed Built in Self Timing Characterizer (BISC) for timing measurements inside critical functional blocks. Thanks to advanced integration, the last CMOS technologies allow high performance in terms of speed. Arithmetic and Logical Units (ALU) are able to work at frequencies greater than few GHz and some memories’ access time is lower than hundreds picoseconds. In the CMOS 40nm analysis case study presented in this paper, a BISC measurement of memories’ access times gives different results than what was expected from simulation. Internal probing becomes mandatory to understand this critical timing issue. A complete comparison is done between the 3 contactless probing techniques available in our laboratory which are the E-Beam Testing (EBT), Time Resolved Emission (TRE) and the recent Laser Voltage Probing (LVP) to highlight strength and weakness of each probing techniques in front of this timing related defect. We demonstrate that the LVP is an inevitable technique to address the nanometer-scale technologies in terms of spatial resolution, low voltage measurements and timing performance.