This paper presents a development in semiconductor device delayering by broad ion beam milling that offers a uniform delayering area on a millimeter scale. A milling area of this size is made possible by the user's ability to position ion beams individually to cover the desired area. This flexibility in ion beam positioning also enables more precise targeting of an area of interest.

This paper describes the detailed sample preparation of a solder joint at the level between a semiconductor package and board. Different sample preparation techniques are described and compared. Preparing and targeting a large sample area containing multiple solder bumps is discussed. The sample preparation methods will then be confirmed by advanced structural characterization and strain measurement. The presence of strain is associated with the development of cracks and delamination at the solder joint interface.

Focused ion beam (FIB) techniques are often used when delayering semiconductor devices. However, using FIB technology for device delayering has limitations. One of these limitations prevents the exposure of a large slope area on the sample, which reveals all layers simultaneously. The delayering process is complex and requires prior process knowledge, such as cross-section architecture, composition, and layer uniformity. This paper discusses advances in semiconductor device deprocessing for product development, failure analysis, and quality control using low-energy, argon broad ion beam (BIB) milling. Ar BIB milling is a practical solution for accurate delayering of advanced microelectronic devices. Results of the spot milling of a whole 300 mm wafer experiment and top-down delayering of wafer pieces experiment show that successful device delayering can be achieved by either spot milling or layer-by-layer milling. These two strategies are easily achieved, for either small wafer pieces or full 300 mm wafer investigation.