Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

Abstract The SEMATECH/SEMI roadmap forecasts increased density requirements for printed circuit board manufacturing to accommodate smaller form factor interconnects, increased pin counts, and routing densities on a range of PCB sizes and thicknesses. As a result, the effect of materials. thermal expansion properties may further impact the structural or physical integrity and subsequent electrical properties for high speed and thermal management requirements. This study demonstrated that various sample coupons selected from PCB boards with different amounts of copper showed a corresponding coefficient of thermal expansion (CTE) correlation in the Z-axis (CTEZ) and can be modeled using a constitutive equation. Moreover, samples were further evaluated from the effect of increasing temperature and showed that the CTE indeed affects copper-interconnect physical structures such as copper vias and barrels in terms of elongation or strain.

Abstract A new generation X-ray laminography (XRL) automated Xray inspection (AXI) tool was evaluated for surface mount technology (SMT) assembly defect detection and was qualified using formal “benchmark” comparative analysis processes. In addition, defect characterization was performed using the XRL AXI system in manual X-ray inspection mode to correlate various failure modes and mechanisms at SMT solder joint interfaces for selected non-destructive failure analyses and technology development. Since ball grid array (BGA) solder joint quality is a great concern in board assembly, test technology development and failure analysis teams explored the use of XRL AXI as a method to detect and monitor BGA ball abnormalities using XRL AXI-generated solder ball images and measurements. It was found that XRL AXI was able to successfully discern differences in the shape, location and diameter of the suspect BGA solder balls from XRL AXI horizontal image planes (slices) for physical failure analysis and reliability issues not previously detected using conventional X-ray transmission or electrical methods. Subsequent metallographic x-sectioning correlated the XRL AXI mages to the physical condition of the suspected second level interconnect (SLI) solder joint location.

Abstract Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.