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N. Dawes
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Proceedings Papers
ISTFA2000, ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis, 393-396, November 12–16, 2000,
Abstract
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Abstract The step into the production line environment is a quantum leap for physical failure analysis (PFA) and will change its work in the near future. Wafer sacrifice for analysis becomes obsolete. The main benefits are: 1. reduction of wafer costs, 2. more splits per development lot, 3. reduced cycle time of analysis and technology development. Machines needed for that purpose are dual beam SEM/FIB tools. In the following we present solutions how PFA in a broad range can be carried out inside of a production line. The analyzed wafers can be fed back into the production flow which results in lower overall costs and the feedback loop to production engineers is dramatically shortened leading to reduced down times of production tools etc. The highest risk that has kept the majority of semiconductor manufacturers from proceeding into this direction is the contamination of the productive wafer with Ga, the FIB beam particle, that may diffuse into productive parts of the wafer during heat cycles after the analysis step. We show that the risk of contamination by Ga and other materials can be controlled.
Proceedings Papers
ISTFA1996, ISTFA 1996: Conference Proceedings from the 22nd International Symposium for Testing and Failure Analysis, 27-35, November 18–22, 1996,
Abstract
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Abstract The paper describes the approach that was developed to cope with the specific difficulties encountered with FIB circuit modification on the 0.5 and 0.35um technologies from a multitude of silicon vendors. This approach involves adaptations in FIB hardware (insulator deposition), software (image alignment), design practice (alignment marks, spare parts, routing recommendations) and FIB practice (procedure for node localisation and contacting, via drill and fill). The latter seems to be a major factor limiting FIB circuit repair feasibility: although it is perfectly feasible to drill deep and small vias (e.g. between minimum spacing overlying metallization), it is not evident to reproducibly fill such holes and obtain a good and reliable via resistance. This limits the minimum size of FIB vias to deep circuit nodes. The developed total approach enables to continue the use of FIB for circuit repair on the new generations of processes, with all the well-known benefits w.r.t. cost savings and Time-To-Market.