Abstract In this paper we discuss the use of Emission Microscopy (EMMI) to examine the events leading to latchup for various Input/Output (I/O) pins of a test chip in order to study the factors that impact latchup sensitivity of VLSI chips. The goal of our study is to identify and characterize the structures that are most prone to latchup in test chips, thus providing countermeasures to be used to improve the overall latchup resistance of commercial chips. As it has been shown in literature [1-3], EMMI can be used to localize areas that are latching up. Here we focus our attention on electrostatic discharge (ESD) into I/O pins, which may lead to latchup inside I/O circuits or in their proximity.

Abstract In this paper we examine the use of the Superconducting Single-Photon Detector (SSPD) [1] for extracting electrical waveforms on an IBM microprocessor fabricated in a 0.13µm technology with 1.2V nominal supply voltage. Although the detector used in our experiments is prototype version of the one discussed in [1] demonstrating lower performance, we will show that it provides a significant reduction in acquisition time for the collection of optical waveforms, thus maintaining the usability of the PICA technique for present and future low voltage technologies.

Abstract Hot-carrier luminescence emission is used to diagnose the cause of excess quiescence current, IDDQ, in a low power circuit implemented in CMOS 7SF technology. We found by optical inspection of the chip that the high IDDQ is related to the low threshold, Vt, device process and in particular to transistors with minimum channel length (0.18 μm). In this paper we will also show that it is possible to gain knowledge regarding the operating conditions of the IC from the analysis of optical emission due to leakage current, aside from simply locating defects and failures. In particular, we will show how it is possible to calculate the voltage drop across the circuit power grid from time-integrated acquisitions of leakage luminescence.